Table 57. MCSI1 Interrupt Mapping
5.3
MCSI1 DMA Request Mapping
Table 58. TDMA Request Mapping—MCSI1
5.4
MCSI2 Pin Description
Table 59. MCSI2 Pin Descriptions
SPRU760B
Incoming Interrupts
MCSI1 TX interrupt
MCSI1 RX interrupt
MCSI1 frame error
Table 58 identifies MCSI1 DMA request lines.
DMA Request Source DMA Request Line—DSP DMA Request Line—MPU
MCSI1 TX
MCSI1 RX
This section provides information specific to MCSI2 on the device.
Table 59 identifies the MCSI2 I/O pins. Figure 59 shows the MCSI2 interface.
Pin
I/O Direction
MCSI2.DIN
In
MCSI2.DOUT
Out
MCSI2.CLK
In/out
MCSI2.SYNC
In/out
Level 2 DSP Interrupt
IRQ_06
IRQ_07
IRQ_10
DMA_REQ_01
DMA_REQ_02
Description
Data input
Data output
Bit clock
Frame synchronization
MCSI1 and MCSI2
Level 2 MPU Interrupt
IRQ_16
IRQ_16
IRQ_16
DMA_REQ_01
DMA_REQ_02
Serial Interfaces
139