Resets - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Reset Architecture

Resets

External Reset

Initialization

This processor has up to three external reset pins depending on the reset

mode. PWRON_RESET is the cold reset for the entire chip.

MPU subsystem reset (this pin has special setup requirements in reset mode

1). RTC_ON_NOFF is a software controlled, power-on reset (unavailable in

reset mode 1).

Reset Mode = 0

Power-up reset

Reset Mode = 0 (Continued)

Power-up reset

Reset Mode = 1

Power-up reset

In reset mode 1, the RTC split-power functionality cannot be used, since the

RTC_ON_NOFF pin is inactive. The real-time clock functionality of the RTC

works correctly in both modes.

In the following sections:

Table 3 summarizes sources and status bits for global resets.

Table 4 covers the resets specific to OMAP3.2 (MPU subsystem).

Table 5 summarizes the peripheral resets for both the MPU and the

If RTC is used, must be considered as battery

power-up reset.

Pulse duration must be two periods of 32 kHz.

Gated by bit 7 of RTC_CTRL_REG. RTC_ON_NOFF

is gated (i.e. disabled) at PWRON_RESET.

Cold reset of MPU subsystem. Does not reset on chip

Pulse duration must be 2 periods of 32 kHz.

Gated by reset mode 1.

Proper pin functionality must be configured (this pin

defaults to MPUIO4).

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