Arm926Ejs Level 2 Interrupt Mapping - Texas Instruments OMAP5912 Reference Manual

Interrupt Overview
Table 4. MPU Level 1 Interrupt Mapping (Continued)
Level 1 Interrupt Line
IRQ_28
IRQ_29
IRQ_30
IRQ_31
†
These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-
dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
‡
These IRQs are available only when the DMA is in OMAP3.1 compatibility mode. See the Multimedia Processor Direct
Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
1.1.4

ARM926EJS Level 2 Interrupt Mapping

Table 5. MPU Level 2 Interrupt Mapping
Level 2 Interrupt Line
IRQ_0
IRQ_1
IRQ_2
IRQ_3
IRQ_4
IRQ_5
IRQ_6
IRQ_7
IRQ_8
IRQ_9
IRQ_10
IRQ_11
†
These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-
dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
16 Interrupts
OMAP 5912 Mapping
Public TIPB abort
Reserved
IRQ_TIMER2
IRQ_LCD_CTRL
DSP and MPU share most of the peripherals. Therefore, almost all of the DSP
level 2 interrupts also go to the MPU level 2 interrupt handlers. The MPU level
2 interrupt handlers are enabled to process 128 more interrupt lines outside
the OMAP gigacell, for a total of 160 interrupt lines. (See Table 5.)
Mapping
FAC
Keyboard
µWIRE TX
µWIRE RX
2
I C
MPUIO
USB HHC 1
USB HHC 2
USB_OTG
Reserved
McBSP3 TX
McBSP3 RX
Sensitivity
Level
−−−−−
Edge
Level
Sensitivity
Level
Edge
Level
Level
Level
Level
Level
Level
Level
−−−−−
Edge
Edge
SPRU757B