Ir Address Checking; Mir Mode; Mir Transmit Frame Format - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

IR Address Checking

MIR Transmit Frame Format

Serial Interfaces

The reception of RXIR input is disabled with DIS_IR_RX bits of the auxiliary

control register (ACREG[5]).

In all IR modes, if address checking has been enabled, only frames intended

for the device are written to the RX FIFO. This is to avoid receiving frames not

meant for this device in a multi-point infrared environment. It is possible to

program two frame addresses that the UART IrDA receives with

XON1/ADDR1 and XON2/ADDR2 registers.

Selecting address1 checking is done by setting EFR[0] to 1, and address2

checking is done by setting EFR[1] to 1. Setting EFR[1:0] to 0 disables all

address checking operations. If both bits are set, the incoming frame is

checked for both private and public addresses.

If address checking is disabled, all received frames are written into the

reception FIFO.

In medium infrared (MIR) mode, data transfer takes place between the LH and

peripheral devices at 0.576 or 1.152M bits/s speed. A MIR transmit frame

begins with start flags (at least 2), followed by a frame data, CRC−16, and ends

with a stop flag.

On transmit, the MIR state machine attaches start flags, CRC−16, and stop

flags. It also looks for 5 consecutive 1s in the frame data and automatically

inserts 0 after them. (This is called bit stuffing.)

On receive, the MIR receive state machine recovers the receive clock,

removes the start flags, destuffs the incoming data, and determines the frame

boundary with reception of the stop flag. It also checks for errors such as frame

abort, CRC error, or frame-length error. At the end of a frame reception, the

LH reads the line status register (LSR) to discover possible errors in the

received frame.

The module transfers data both ways, but when the device is transmitting,

hardware automatically disables the IR RX circuitry. Refer to Table 104,

Auxiliary Control Register Bit 5, for a description of the logical operation of all

three modes, SIR, MIR, and FIR.

Table of Contents