Ramset Memory Organization; Instruction Cache Structure - Texas Instruments OMAP5912 Reference Manual

block consists of 512 cache lines containing 16 bytes (4 words) of instructions
from consecutive addresses. Control and status bits are associated with each
cache line to support virtual to physical mapping and cache control/operation.
A 24-bit program virtual address is parsed into word, line index, and TAG
sections, as shown in Figure 5. The line index determines which cache entry
to test. The TAG is used to check the cache contents against the requested
instruction address. The word field determines which bytes on the cache line
to fetch when a cache hit occurs. A two-way set-associative cache structure
has two 8K-byte RAM blocks in parallel, so there are two cache lines and two
TAGs associated with each line number defined by the index. When an
instruction is written in the cache, its TAG is also written.
Figure 5. Virtual Address Mapped to Cache Line
23
TAG
WORD field size = 4 bits
INDEX field size = 9 bits
TAG field size = 11 bits
3.2.2

Ramset Memory Organization

Ramset memory is a special type of cache memory. The 8K-byte memory
block is divided into two 4K-byte sections (called ½ ramset) that can be
controlled independently. Because the ½ ramset memory block is 4K bytes
long and the line size is still four words, there are 256 lines in each module.
This makes the INDEX field size 8 bits and the TAG field size 12 bits. In ramset
memory there is only a single TAG for each 4K-byte block as opposed to each
line in regular cache memory. This organization allows the user to dynamically
remap 4K-byte memory blocks from external to internal memory (once the ½
ramset memory has been filled).
3.2.3

Instruction Cache Structure

The I-cache block has status bits associated with each cache line. A line-valid
bit (LVB) defines whether or not the data in the cache line has valid instructions
resulting from a fetch from external program memory. When the cache is first
enabled (or after flushing), all the cache lines in the data array and TAGs in the
TAG array are random. The line valid bit is set to 0 for all cache entries. When
an external program fetch occurs and the corresponding line valid bit is zero,
a cache miss occurs automatically. Figure 6 shows the cache structure for a
direct-mapped cache block.
Figure 6. Cache Structure—Direct-Mapped Cache Block
TAG
array
SPRU750A
13 12
Data−mapped
Line
valid bit
4 3
INDEX
Data array
DSP Subsystem
DSP Memory
0
WORD
Line number
25
0