Control Of External Clock And Voltage Supplies - Texas Instruments OMAP5912 Reference Manual

Power Management User Services
Figure 25. OMAP5912 Wake-Up Management
Standby wait for interruption signal deassertion (4)
External
clocks, on (2)
U
External
clock request
L
(1)
P
D
System clock
32 MHz
3.4.4

Control of External Clock and Voltage Supplies

88 Power Management
Wake up interrupt signal (3)
Chip idle
Control
request (2)
registers
chip
idle (5)
and
OMAP5912
Reference
clock, cut (2)
Clock
reset
Wake up event signal (1)
32-kHz
clock
The ULPD provides the LOW_PWR and LOW_PWR signals to control the
activation or the shutdown of the external clock and the core voltage supplies.
-
LOW_PWR indicates to external devices that the system clock can be
shut down (in external clock mode).
-
LOW_PWR drives the external core voltage supply in low voltage (1.1 V)
operations. The behavior of the LOW_PWR signal is set by software and
can be configured to allow two types of operation:
J
Reduction of leakage current in deep sleep mode
J
Low-voltage operation at reduced clock frequency (dynamic voltage
scaling)
To enable the operation at reduced clock frequency under external low-voltage
supplies, the LOW_PWR signal is set by software through the ULPD power
control register (POWER_CTRL_REG bits 1, 4, 10, and 11). Figure 26
summarizes the LOW_PWR signal behavior.
ARM926EJS
MPU (CP15) Instruction
Standby decoded
idle x request
idle x acknowledge
idle x request
idle x acknowledge
idle x request
idle x acknowledge
idle x request deassertion(6)
idle x acknowledge (4)
OMAP5912
module
OMAP5912
OMAP5912
OMAP5912
module x
SPRU753A