Transmission Clock Frequency; Mcsi Configuration - Texas Instruments OMAP5912 Reference Manual

Transmission Clock Frequency

4.1.2 Sample Setup for Communication µ-Law Interface Using Interrupts

MCSI Configuration

Transmit Data Loading (TX_INT ISR)
SPRU760B
In master mode, the clock frequency is derived from the 12-MHz master clock
and can be programmed from 5.8 kHz to 6 MHz in increments of 83 ns.
Control bit:
CLOCK_FREQUENCY_REG(10:0) = CLK_FREQ
(2<=CLK_FREQ <= 2047)
with
(t = t * CLK_FREQ)
CLK 12MHz
An example of communication µ-law interface setup using interrupts follows.
DSP_Write(0x0000) = CONTROL_REG (disable MCSI for setup)
-
DSP_Write(0x0007) = MAIN_PARAMETERS_REG (set up MCSI per
-
configuration below)
Bit 15-14 (00b): No DMA
J
Bit 10 (0b): Positive polarity for frame
J
Bit 9 (0b): Normal synchronization mode
J
Bit 8 (0b): Short framing
J
Bit 7 (0b): Single channel
J
Bit 6 (0b): Slave mode
J
Bit 5 (0b): Burst mode
J
Bit 4 (0b): Positive edge for clock
J
Bit 3-0 (0111b): 8-bit data
J
DSP_Write(0x0700) = INTERRUPTS_REG (all interrupts are enabled)
-
DSP_Write(0x0000) = OVER_CLOCK_REG
-
DSP_Write(0x0001) = CONTROL_REG (start MCSI)
-
DSP_Write = TX_REG
-
Multichannel Serial Interfaces
Serial Interfaces 117