External Memory Interface; Emif Global Control Register - Texas Instruments OMAP5912 Reference Manual

6

External Memory Interface

6.1

EMIF Global Control Register

Table 17. EMIF Global Control Register (EMIF GCR)
Bit Name
15−12 Reserved
11−8 Reserved
7 WPE
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
SPRU750A
-
1: On
The MPUI RAM is owned only by the host processor. If you set the HOM_R
bit, a request for host-only mode is sent to the MPUI. If the MPUI sets the
HOM_R bit, the setting indicates that the host processor has exclusive
ownership of the MPU RAM.
The external memory interface (EMIF) is a DSP subsystem module that gives
the DSP access to the shared system memory managed by the traffic
controller. The EMIF interfaces directly to a 32-bit-wide system bus. This bus
can operate at the CPU clock rate with sustained throughput during burst
accesses. The EMIF has two control registers for user configuration:
-
EMIF global control register (GCR)
-
EMIF global reset register (GRR)
EMIF does not have support for 8 bit DMA read line.
The EMIF global control register (EMIF_GCR) configures the general
operation of the EMIF module. The EMIF GCR appears at word address
0x0800 in the DSP I/O space.
Function
Write posting enable
WPE=0, write posting is disabled (for debug).
WPE=1, write posting is enabled.
External Memory Interface
Reset
Value
Type
R 0
RW 0
RW 0
RW 0
RW 1
R 0
R x
R x
DSP Subsystem 57