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Figure 2.
Read Operation
Write 0x70,
NND_COMMAND_SEC
Status = read
NND_ACCESS
Bit 6
= 1
(Ready/Busy)
?
Write 0x00,
NND_COMMAND_SEC
2.1.2
Write Operation
SPRU756A
Write start address, NND_ADDR_SRC
No
First, the command 0x00 or 0x01 or 0x50 is driven on the bus with qualifier CLE
high. This is to select which area (A, B, or C) to program. Then, the command
0x80 is driven on the bus with the qualifier CLE being high. Last, the start
address is driven byte-by-byte, least significant byte first, with the qualifier ALE
being high (see Table 3).
Writing data in the NAND controller access register (NND_ACCESS) places
the data on the bus and asserts a negative pulse on WE_ (CLE and ALE are
low). After the last data has been driven, a command 0x10 is sent to terminate
the flow of data. The NFMC drives R/B_ to low during the programming of
NFMC (from its internal page register to memory cell) and R/B_ goes back to
high, asserting an interrupt. This interrupt bit is cleared by software using the
scheme shown in Table 30. The NFMC is now ready for the next operation.
The result of the operation can be checked with a read status operation
(sending the command 0x70 or 0x71) to the NFMC
Start read
Write 0x00, NND_COMMAND or
Write 0x01, NND_COMMAND or
Write 0x50, NND_COMMAND
Wait for t r time
Read data, NND_ACCESS
Read NND_ECCx registers
(OCP access)
Read spare area
ECC check
End read
Memory Interfaces for the EMIFS
Writing to this register, sends also
the address to the flash core.
To select the area:
− 0x00: 0−255
− 0x01: 256−511
− 0x50: 512−527
There is a latency after the address
is sent, for the to be ready.
This can be done with:
− An interrupt
− Reading the NAND flash status
register
− Polling the ready bit in the
NND_READY register of the
NAND flash controller
The access to NND_ACCESS will
trigger the RE_SIGNAL to the
NAND flash.
While reading, accumulate the
line and row parities for ECC
computation. ECC is stored
in registers
Use same procedure to read
spare area
ECC check and eventual bit repair
done in software
Memory Interfaces
25
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