Reset Architecture; Reset Modes And Clocking Options - Texas Instruments OMAP5912 Reference Manual

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Reset Architecture

1.1

Reset Modes and Clocking Options

Table 1. Clocking Options with respect to Reset Modes
OSC1_IN support via crystal?
OSC1_IN support w/external clock source?
SYS_CLK_IN support w/external clock source?
OSC1_IN support via crystal?
OSC1_IN support w/external clock source?
SYS_CLK_IN support w/external clock source?
SPRU752B
This document describes the reset architecture, the configuration, and the
initialization of the OMAP5912 multimedia processor. All references to device
package ball number in this document refer to the ZZG package. Please see
the data manual (SPRS231) for complete pinout information for both the ZZG
and ZDY packages.
The reset architecture describes the reset signal distribution to the peripherals.
Reset mode 0 has several clocking options while reset mode 1 is much more
restrictive. It is important to examine Table 1 when determining which reset
mode to use.
Reset Mode = 0
Reset Mode = 1
It is critical to understand that certain systems and functionalities may not
be available in both reset modes. The selection between reset modes
should be made at an early stage in the development cycle. Generally,
reset mode 0 is flexible while reset mode 1 is more restrictive. Reset
mode is based on the value of the RESET_MODE pin (sampled on the
rising edge of PWRON_RESET).
In addition to affecting the clocking options, reset mode affects many other
features such as pin multiplexing at reset time, I/O direction and impedance
at reset time, and more. Throughout this document, the reset mode will be
specified when it is relevant to the discussion.
Initialization
12 MHz 13 MHz
Yes Yes
Yes Yes
No No
12 MHz 13 MHz
No No
No No
No No
Initialization
19.2 MHz
Yes
Yes
No
19.2 MHz
No
No
Yes
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