Synchronized Channel - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Table 17. Associated Physical Channels Per Logical Channel Type

Synchronized Channel

The fourth channel, PCh-D, is specifically designed for transfers to the display

and can only be used by the dedicated LCh-D. LCh-D must always be

configured as type LCh-D.

There are six global registers: PCh status register, PCh ID register, and one

PCh status register per PCh channel. See respective register descriptions for

more details.

LCh Types Supporting Syn-

chronized Channels

A synchronized channel (hardware activated) is a channel that only becomes

active when it is enabled by software and subsequently receives a DMA

request signal either from an peripheral or from an dedicated ball. There are

31 possible hardware DMA request sources, 1 to 31. A hardware DMA request

cannot be shared between several concurrent channels (enabled and active).

However, a hardware DMA request can be shared between different channels

if they are part of a chain. The peripheral hardware request associated with

each of the 31 system DMA request is controllable through MPU GDMA

handler configuration.

Software must program the five SYNC bits located in the channel control

channel. The logical channel becomes a synchronized channel when this field

is set to reflect the number of the request line. Remember that no DMA request

can be mapped as 0, which is reserved to specify a nonsynchronized transfer.

PCh Assigned

PCh-0 or PCh-1

(dynamic allocation)

Direct Memory Access (DMA) Support

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