Channel Source Start Address - Texas Instruments OMAP5912 Reference Manual

Table 115. Channel Status Registers (DMA_CSR0...DMA_CSR5) (Continued)
Bit Name
1 DROP
0 TOUT
4.23.2

Channel Source Start Address

SPRU755B
Function
Synchronization event drop status bit. If a DMA
synchronization event occurs again before the
DMA controller is done servicing the previous DMA
request, an error has occurred (a synchronization
event drop). The DMA controller sets DROP only if
DROP_IE = 1 in DMA_CICR and a
synchronization event drop has occurred in the
channel.
0: No event drop occurred or the the DROP bit has
been cleared.
1: A synchronization event drop has occurred. A
channel interrupt request has been sent to the
CPU.
Time-out status bit. The DMA controller sets TOUT
only if TOUT_IE = 1 in DMA_CICR and time-out
error has occurred at the source port or the
destination port of the channel:
0: A time-out error has not occurred, or TOUT has
been cleared.
1: A time-out error has occurred. A bus-error
interrupt request has been sent to the DSP CPU.
This register is written by the DMA controller to reflect the channel status. It
can be read by the processor to monitor which events have occurred. All status
bits other than SYNC must be individually enabled in DMA_CICR for their
status to be registered. The SYNC bit is always set after its synchronization
event occurs. After a program read of DMA_CSR, all bits are automatically
cleared within two DSP clock cycles. The bits are not cleared if read via
hardware emulator/debugger.
Each channel has two source start address registers: DMA_CSSA_L and
DMA_CSSA_U. For the first access to the source port of the channel, the DMA
controller generates a byte address by concatenating the contents of the two
I/O mapped registers.
Source address DMA_CSSA_U:DMA_CSSA_L
Direct Memory Access (DMA) Support
DSP DMA
Type Reset
R 0
R 0
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