Timer Interrupt Control - Texas Instruments OMAP5912 Reference Manual

Dual-Mode Timer
Figure 6. Timing Diagram of Pulse-Width Modulation With SCPWM Bit = 0
Timer clock
Internal overflow pulse
Internal match pulse
Timer PWM (TRG = 01 & PT = 0)
Timer PWM (TRG = 10 & PT = 0)
Timer PWM (TRG = 10 & PT = 1)
Timer PWM (TRG = 01 & PT = 1)
Figure 7. Timing Diagram of Pulse-Width Modulation With SCPWM Bit = 1
Timer clock
Internal overflow pulse
Internal match pulse
Timer PWM (TRG = 01 & PT = 0)
Timer PWM (TRG = 10 & PT = 0)
Timer PWM (TRG = 10 & PT = 1)
Timer PWM (TRG = 01 & PT = 1)
4.7

Timer Interrupt Control

36 Timers
In Figure 7 TCLR (SCPWM bit) is set to 1.
The timer can issue an overflow interrupt, a timer match interrupt, and a timer
capture interrupt. Each internal interrupt source can be independently
enabled/disabled in the interrupt enable register TIER. When the interrupt
event has been issued, the associated interrupt status bit is set in the timer
status register (TISR). The pending interrupt event is reset when the set status
bit is overwritten by a 1. Reading the interrupt status register and writing the
value back allows fast interrupt acknowledge.
SPRU759B