Local Power Management - Texas Instruments OMAP5912 Reference Manual

Table 44. Idle Status Register (ISTR) (Continued)
MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x02 (word)
Bit Name
2 RHEA_IDLECACHE_TR CACHE idle status.
1 RHEA_IDLEDMA_TR
0 RHEA_IDLECPU_TR

Local Power Management

SPRU753A
Function
DMA idle status.
CPU idle status.
The TIPB bridge performs some checks when the DSP idle instruction is
executed:
-
If the DPLL bit is set to 1 in the ICR and one or more of the CPU, DMA,
EMIF, or CACHE bits are set to 0, a bus error is generated and the idle
request is canceled.
-
Before setting the DPLL into idle, the TIPB bridge checks whether DMA,
EMIF, and CACHE are inactive. If they are not, it waits for these blocks to
become inactive before entering idle mode.
All peripherals are part of the same domain. Therefore, when the peripherals
domain is put in idle mode, the clocks of all peripherals are stopped.
TIPB and MPU blocks are not part of any domain. The DPLL must be
disabledto put them in idle mode.
If some blocks are in idle mode but both the CPU and the DPLL are not, the
program flow is maintained. It is thus possible to exit from idle mode by writing
in the ICR register and by executing an idle instruction. This is the only wake
procedure under software control; the other wake procedures are under
hardware control.
The EMIF global control register (see Table 45) allows control of the SDRAM
clock (it can be enabled or stopped) and the SBSRAM clock (it can be enabled
or stopped and the frequency can also be divided by 2). The EMIF external bus
can also be placed in low-power state with this register.
Power Management User Services
R/W
R
R
R
Power Management
Reset
0
0
0
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