Table of Contents
Advertisement
Table 25. Channel Addresses and Access Types
3.1.12
Interrupt Generation
SPRU755B
Frame
Number j
Access
0
2
1
2
2
2
3
1
4
1
5
1
6
1
7
1
8
1
9
End of transfer
In this example the first word16 is not packed to word32 because the address
is not aligned on word32. The next accesses bursts 4x32 bits, because burst
is enabled, constant addressing is not used, EI = 1, address is 4x32 bits burst
aligned, and enough data is left in the frame (16 bytes). All other transfers are
word16 single accesses or 32 bit packed accesses. There are no more bursts
because the next time the address is burst aligned, there is not enough data
left in the frame (less than 16 bytes).
LCh Types Supporting this Feature
LCh Types Supporting this Feature
Each generic LCh can generate six different interrupts. The following interrupt
sources can be programmed:
End of block: The last byte of the transfer has been written into
-
destination, enabled with bit BLOCK_IE in register DMA_CICR.
End of frame: The last byte of the current frame has been written into
-
destination, enabled with bit FRAME_IE in register DMA_CICR.
Half of frame: The middle byte of current frame has been written into
-
destination, enabled with bit HALF_IE in register DMA_CICR.
Start of last frame: The first word of the last frame has been written into
-
destination, enabled with bit LAST_IE in register DMA_CICR.
Request collision: Two new DMA requests occurred before the end of
-
service of previous request, enabled with DROP_IE bit in register
DMA_CICR.
Element
Address
Number i
[byte]
10
10
9-2
12
1
28
10
42
9,8
44
7,6
48
5,4
52
3,2
64
1
68
2D
P
√
√
Direct Memory Access (DMA) Support
System DMA
Access Type
16 bits
4x32 bits
16 bits
16 bits
32 bits
32 bits
32 bits
32 bits
16 bits
PD
G
D
√
√
√
57
Advertisement
Chapters
Table of Contents
