Page 1 MSP430x4xx Family User’s Guide 2005 Mixed Signal Products SLAU056E...
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Page 3: Read This First
About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family.
Page 4 Glossary Glossary ACLK Auxiliary Clock Analog-to-Digital Converter Brown-Out Reset Bootstrap Loader Central Processing Unit Digital-to-Analog Converter Digitally Controlled Oscillator See FLL+ Module Destination Frequency Locked Loop General Interrupt Enable INT(N/2) Integer portion of N/2 Input/Output Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode Memory Address Bus...
Page 5 Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition −0,−1 −(0),−(1) Condition after POR Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0...
Page 7: Table Of Contents
Introduction Architecture Flexible Clock System ............Embedded Emulation .
Page 8 Contents 3.3.5 Indirect Register Mode 3.3.6 Indirect Autoincrement Mode 3.3.7 Immediate Mode Instruction Set ............3.4.1 Double-Operand (Format I) Instructions 3.4.2...
Page 9 Hardware Multiplier ............. Hardware Multiplier Introduction Hardware Multiplier Operation 7.2.1...
Page 10 Contents 11 Basic Timer1 ..............11.1 Basic Timer1 Introduction 11.2...
Page 11 15 USART Peripheral Interface, SPI Mode 15.1 USART Introduction: SPI Mode 15.2 USART Operation: SPI Mode 15.2.1 USART Initialization and Reset 15.2.2 Master Mode ............15.2.3 Slave Mode .
Page 12 Contents 19 LCD_A Controller ............. . 19.1 LCD_A Controller Introduction 19.2 LCD_A Controller Operation 19.2.1 LCD Memory...
Page 13 22 SD16_A ............... 22.1 SD16_A Introduction 22.2 SD16_A Operation .
Page 14: Introduction
This chapter describes the architecture of the MSP430. Topic Architecture ..........Flexible Clock System .
Page 15: Architecture
(MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x4xx family include: Ultralow-power architecture extends battery life 0.1- A RAM retention 0.8- A real-time clock mode...
Page 16: Embedded Emulation
Figure 1−1. MSP430 Architecture Clock ACLK Flash/ System SMCLK MCLK MAB 16-Bit RISC CPU 16-Bit MDB 16-Bit JTAG ACLK SMCLK Watchdog 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an application are supported.
Page 17: Address Space
Address Space 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words.
Page 18: Peripheral Modules
1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules.
Page 19 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, and operating modes. Topic System Reset and Initialization Interrupts ........... . .
Page 20: System Resets, Interrupts, And Operating Modes
System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
Page 21: Brownout Reset (Bor)
2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the V device by triggering a POR signal when power is applied or removed. The operating levels are shown in Figure 2−2.
Page 22: Device Initial Conditions After System Reset
System Reset and Initialization 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: The RST/NMI pin is configured in the reset mode. I/O pins are switched to input mode as described in the Digital I/O chapter. Other peripheral modules and registers are initialized as described in their respective chapters in this manual.
Page 23: Interrupts
2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously.
Page 24: Non)-Maskable Interrupts (Nmi)
System Reset and Initialization 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset.
Page 25 Figure 2−4. Block Diagram of (Non)-Maskable Interrupt Sources ACCV ACCVIFG FCTL1.1 ACCVIE IE1.5 Clear RST/NMI NMIIFG IFG1.4 Clear NMIIE IE1.4 Clear OSCFault OFIFG IFG1.1 OFIE IE1.1 Clear NMI_IRQA IRQA: Interrupt Request Accepted System Reset and Initialization Flash Module KEYV System Reset Generator WDTTMSEL WDTNMIES...
Page 26 System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator. The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault.
Page 27: Maskable Interrupts
Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2−5. Figure 2−5.
Page 28 System Reset and Initialization Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual. 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-maskable interrupts to be requested.
Page 29 Return From Interrupt The interrupt handling routine terminates with the instruction: (return from an interrupt service routine) RETI The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−7. 1) The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc.
Page 30: Interrupt Vectors
System Reset and Initialization 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in Table 2−1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine.
Page 31: Operating Modes
2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−9. The operating modes take into account three different needs: Ultralow-power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2−8.
Page 32 Operating Modes Figure 2−9. MSP430x4xx Operating Modes For Basic Clock System WDT Active, Time Expired, Overflow WDTIFG = 1 WDTIFG = 1 WDT Active, Security Key Violation CPUOFF = 1 SCG0 = 0 SCG1 = 0 LPM0 CPU Off, FLL+ On,...
Page 33: Entering And Exiting Low-Power Modes
2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: Enter interrupt service routine: The PC and SR are stored on the stack The CPUOFF, SCG1, and OSCOFF bits are automatically reset Options for returning from the interrupt service routine: The original SR is popped from the stack, restoring the previous operating mode.
Page 34: Principles For Low-Power Applications
Principles for Low Power Applications 2.4 Principles for Low Power Applications Often, the most important factor for reducing power consumption is using the MSP430’s clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 A typical with both a real-time clock function and all interrupts active.
Page 35: Risc 16-Bit Cpu
This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic CPU Introduction ..........CPU Registers .
Page 36: Cpu Introduction
CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: RISC architecture with 27 instructions and 7 addressing modes.
Page 37 Figure 3−1. CPU Block Diagram MDB − Memory Data Bus Zero, Z Carry, C Overflow, V Negative, N Memory Address Bus − MAB R0/PC Program Counter 0 R1/SP Stack Pointer R2/SR/CG1 Status R3/CG2 Constant Generator General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose...
Page 38: Cpu Registers
CPU Registers 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed.
Page 39: Stack Pointer (Sp)
3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
Page 40: Status Register (Sr)
CPU Registers 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remain- ing combinations of addressing modes are used to support the constant gen- erator.
Page 41: Constant Generator Registers Cg1 And Cg2
3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3−2. Table 3−2.
Page 42: General−Purpose Registers R4 - R15
CPU Registers 3.2.5 General−Purpose Registers R4 - R15 The twelve registers, R4−R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions as shown in Figure 3−7. Figure 3−7.
Page 43: Addressing Modes
3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3−3 describe the contents of the As (source) and Ad (destination) mode bits. Table 3−3.
Page 44: Register Mode
Addressing Modes 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Length: Operation: Comment: Example: Before: 0A023h 0FA15h Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result.
Page 45: Indexed Mode
3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 00006h 0FF14h 00002h 04596h 0FF12h 01094h 0xxxxh 01092h 05555h 0xxxxh 01090h 01084h 0xxxxh 01082h 01234h 0xxxxh 01080h Assembler Code Content of ROM...
Page 46: Symbolic Mode
Addressing Modes 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 0FF14h 0F102h 0FF12h 0F018h 0F016h 0F014h 01116h 01114h 05555h 01112h 3-12 RISC 16-Bit CPU Assembler Code Content of ROM MOV EDE,TONI...
Page 47: Absolute Mode
3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Length: Operation: Comment: Example: Before: 0FF16h 0FF14h 0FF12h 0F018h 0F016h 0F014h 01116h 01114h 01112h This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address.
Page 48: Indirect Register Mode
Addressing Modes 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Length: Operation: Comment: Example: Before: Address Space 0xxxxh 0FF16h 0000h 0FF14h 04AEBh 0FF12h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0FA30h 0xxxxh 002A8h 0xxh 002A7h...
Page 49: Indirect Autoincrement Mode
3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Length: Operation: Comment: Example: Before: Address Space 0xxxxh 0FF18h 0FF16h 00000h 0FF14h 04ABBh 0xxxxh 0FF12h 0FA34h 0xxxxh 0FA32h 05BC1h 0xxxxh 0FA30h 010AAh 0xxxxh 010A8h...
Page 50: Immediate Mode
Addressing Modes 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10.Immediate Mode Description Length: Operation: Comment: Example: Before: Address Space 0FF16h 0FF14h 0FF12h 010AAh 010A8h 010A6h 3-16 RISC 16-Bit CPU Assembler Code Content of ROM #45h,TONI MOV @PC+,X(PC) X = TONI −...
Page 51: Instruction Set
3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction.
Page 52: Double-Operand (Format I) Instructions
Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format Op-code Table 3−11 lists and describes the double operand instructions. Table 3−11. Double Operand Instructions Mnemonic S-Reg, MOV(.B) ADD(.B) ADDC(.B) SUB(.B) SUBC(.B) CMP(.B)
Page 53: Single-Operand (Format Ii) Instructions
3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format Table 3−12 lists and describes the single operand instructions. Table 3−12.Single Operand Instructions Mnemonic RRC(.B) RRA(.B) PUSH(.B) SWPB CALL RETI The status bit is affected −...
Page 54: Jumps
Instruction Set 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format Op-code Table 3−13 lists and describes the jump instructions. Table 3−13.Jump Instructions Mnemonic JEQ/JZ JNE/JNZ Conditional jumps support program branching relative to the PC and do not affect the status bits.
Page 55 ADC[.W] Add carry to destination ADC.B Add carry to destination Syntax ADC.B Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise...
Page 56 Instruction Set ADD[.W] Add source to destination ADD.B Add source to destination Syntax src,dst ADD.B src,dst Operation src + dst −> dst Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise...
Page 57 ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC ADDC.B Operation src + dst + C −> dst Description The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected.
Page 58 Instruction Set AND[.W] Source AND destination AND.B Source AND destination Syntax AND.B Operation src .AND. dst −> dst Description The source operand and the destination operand are logically ANDed. The result is placed into the destination. Status Bits N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 59 BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax BIC.B Operation .NOT.src .AND. dst −> dst Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
Page 60 Instruction Set BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax BIS.B Operation src .OR. dst −> dst Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected.
Page 61 BIT[.W] Test bits in destination BIT.B Test bits in destination Syntax Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. Status Bits N: Set if MSB of result is set, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
Page 62 Instruction Set * BR, BRANCH Branch to ... destination Syntax Operation dst −> PC Emulation dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction.
Page 63 CALL Subroutine Syntax CALL Operation SP − 2 Description A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction.
Page 64 Instruction Set * CLR[.W] Clear destination * CLR.B Clear destination Syntax CLR.B Operation 0 −> dst Emulation MOV.B Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. Example Register R5 is cleared. Example RAM byte TONI is cleared.
Page 65 * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 66 Instruction Set * CLRN Clear negative bit Syntax CLRN Operation (.NOT.src .AND. dst −> dst) Emulation #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction.
Page 67 * CLRZ Clear zero bit Syntax CLRZ Operation (.NOT.src .AND. dst −> dst) Emulation #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. Status Bits N: Not affected Z: Reset to 0...
Page 68 Instruction Set CMP[.W] Compare source and destination CMP.B Compare source and destination Syntax CMP.B Operation dst + .NOT.src + 1 (dst − src) Description The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored;...
Page 69 * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC DADC.B Operation dst + C −> dst (decimally) Emulation DADD DADD.B Description The carry bit (C) is added decimally to the destination. Status Bits N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise...
Page 70 Instruction Set DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD DADD.B Operation src + dst + C −> dst (decimally) Description The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs.
Page 71 * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC.B Operation dst − 1 −> dst Emulation #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 72 Instruction Set * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD DECD.B Operation dst − 2 −> dst Emulation #2,dst Emulation SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 73 * DINT Disable (general) interrupts Syntax DINT Operation (0FFF7h .AND. SR Emulation #8,SR Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status Bits Status bits are not affected.
Page 74 Instruction Set * EINT Enable (general) interrupts Syntax EINT Operation (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR.
Page 75 * INC[.W Increment destination * INC.B Increment destination Syntax INC.B Operation dst + 1 −> dst Emulation #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise...
Page 76 Instruction Set * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD INCD.B Operation dst + 2 −> dst Emulation #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise...
Page 77 * INV[.W] Invert destination * INV.B Invert destination Syntax INV.B Operation .NOT.dst −> dst Emulation #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 78 Instruction Set Jump if carry set Jump if higher or same Syntax label label Operation If C = 1: PC + 2 If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 79 JEQ, JZ Jump if equal, jump if zero Syntax label, Operation If Z = 1: PC + 2 If Z = 0: execute following instruction Description The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 80 Instruction Set Jump if greater or equal Syntax label Operation If (N .XOR. V) = 0 then jump to label: PC + 2 If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 81 Jump if less Syntax label Operation If (N .XOR. V) = 1 then jump to label: PC + 2 If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 82 Instruction Set Jump unconditionally Syntax label Operation PC + 2 offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces the BRANCH instruction in the range of −511 to +512 words relative to the current program counter.
Page 83 Jump if negative Syntax label Operation if N = 1: PC + 2 if N = 0: execute following instruction Description The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed.
Page 84 Instruction Set Jump if carry not set Jump if lower Syntax label label Operation if C = 0: PC + 2 if C = 1: execute following instruction Description The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 85 Jump if not equal Jump if not zero Syntax label label Operation If Z = 0: PC + 2 If Z = 1: execute following instruction Description The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 86 Instruction Set MOV[.W] Move source to destination MOV.B Move source to destination Syntax MOV.B Operation src −> dst Description The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status Bits Status bits are not affected.
Page 87 * NOP No operation Syntax Operation None Emulation #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. The NOP instruction is mainly used for two purposes: To fill one, two, or three memory words To adjust software timing...
Page 88 Instruction Set * POP[.W] Pop word from stack to destination * POP.B Pop byte from stack to destination Syntax POP.B Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation Emulation MOV.B Description The stack location pointed to by the stack pointer (TOS) is moved to the destination.
Page 89 PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH PUSH.B Operation SP − 2 Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status Bits Status bits are not affected.
Page 90 Instruction Set * RET Return from subroutine Syntax Operation SP + 2 Emulation @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call.
Page 91 RETI Return from interrupt Syntax RETI Operation SP + 2 SP + 2 Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two.
Page 92 Instruction Set * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA.B Operation C <− MSB <− MSB−1 ... LSB+1 <− LSB <− 0 Emulation dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 3−14. The MSB is shifted into the carry bit (C) and the LSB is filled with 0.
Page 93 * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC.B Operation C <− MSB <− MSB−1 ... LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3−15. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Page 94 Instruction Set RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA.B Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, Description The destination operand is shifted right one position as shown in Figure 3−16. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB.
Page 95 RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax Operation C −> MSB −> MSB−1 ... LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). Figure 3−17.
Page 96 Instruction Set * SBC[.W] Subtract source and borrow/.NOT. carry from destination * SBC.B Subtract source and borrow/.NOT. carry from destination Syntax SBC.B Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC #0,dst SUBC.B #0,dst Description...
Page 97 * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example Emulation of the decimal subtraction: Subtract R5 from R6 decimally...
Page 98 Instruction Set * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. RISC 16−Bit CPU 3-64...
Page 99 * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Instruction Set RISC 16−Bit CPU 3-65...
Page 100 Instruction Set SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax src,dst SUB.B src,dst Operation dst + .NOT.src + 1 −> dst [(dst − src −> dst)] Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1.
Page 101 SUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destination SUBC.B,SBB.B Subtract source and borrow/.NOT. carry from destination Syntax SUBC src,dst src,dst SUBC.B src,dst Operation dst + .NOT.src + C −> dst (dst − src − 1 + C −> dst) Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C).
Page 102 Instruction Set SWPB Swap bytes Syntax SWPB Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 103 Extend Sign Syntax Operation Bit 7 −> Bit 8 ... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
Page 104 Instruction Set * TST[.W] Test destination * TST.B Test destination Syntax TST.B Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP.B Description The destination operand is compared with zero. The status bits are set accord- ing to the result. The destination is not affected. Status Bits N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise...
Page 105 XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax XOR.B Operation src .XOR. dst −> dst Description The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. Status Bits N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise...
Page 106: Instruction Cycles And Lengths
Instruction Set 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles Table 3−14 lists the CPU cycles for interrupt overhead and reset.
Page 107 Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3−16.Format I Instruction Cycles and Lengths Addressing Mode @Rn+ x(Rn) &EDE No. of Length of Cycles Instruction x(Rm) &EDE x(Rm)
Page 108: Instruction Set Description
Instruction Set 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in Table 3−17. Figure 3−20. Core Instruction Map 0xxx 4xxx 8xxx Cxxx 1xxx RRC.B SWPB RRA.B 14xx 18xx 1Cxx 20xx 24xx 28xx...
Page 109 Table 3−17.MSP430 Instruction Set Mnemonic Description † Add C to destination ADC(.B) Add source to destination ADD(.B) src,dst Add source and C to destination ADDC(.B) src,dst AND source and destination AND(.B) src,dst Clear bits in destination BIC(.B) src,dst Set bits in destination BIS(.B) src,dst Test bits in destination...
Page 110: Fll+ Clock Module
FLL+ Clock Module The FLL+ clock module provides the clocks for MSP430x4xx devices. This chapter discusses the FLL+ clock module. The FLL+ clock module is implemented in all MSP430x4xx devices. Topic FLL+ Clock Module Introduction FLL+ Clock Module Operation ........
Page 111 4.1 FLL+ Clock Module Introduction The frequency-locked loop (FLL+) clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware. The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch crystal frequency.
Page 112 Figure 4−1. MSP430x44x and MSP430x43x Frequency-Locked Loop XTS_FLL OSCOFF LFOff XOUT LFXT1 Oscillator XCAPxPF /(N+1) SCG1 /1/2/4/8 XT20FF XT2IN XT2OUT XT2 Oscillator FLL_DIVx Divider /1/2/4/8 f Crystal SCG0 Enable Reset XT1Off 10−bit Frequency Integrator − Generator Modulator FLLDx DCOPLUS f DCO Divider f DCO/D FLL+ Clock Module...
Page 113 Figure 4−2. MSP430x42x and MSP430x41x Frequency-Locked Loop OSCOFF XTS_FLL LFOff XOUT LFXT1 Oscillator XCAPxPF /(N+1) SCG1 Generator FLLDx Divider /1/2/4/8 FLL+ Clock Module FLL_DIVx Divider /1/2/4/8 f Crystal SCG0 Enable Reset XT1Off 10−bit Frequency Integrator − Modulator DCOPLUS f DCO f DCO/D ACLK/n ACLK...
Page 114: Fll+ Clock Module Operation
MOV.B #(64−1),&SCFQTL MOV.B #FN_2,&SCFIO 4.2.1 FLL+ Clock features for Low-Power Applications Conflicting requirements typically exist in battery powered MSP430x4xx applications: Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing...
Page 115: Lfxt1 Oscillator
FLL+ Clock Module Operation 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connects to XIN and XOUT without any external components. The LFXT1 oscillator supports high-speed crystals or resonators when in HF mode (XTS_FLL = 1).
Page 116: Digitally-Controlled Oscillator (Dco)
4.2.4 Digitally-Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N, the lowest 7 bits of the SCFQCTL register. The DCOPLUS bit sets the f bits configure the divider, D, to 1, 2, 4 or 8.
Page 117: Dco Modulator
FLL+ Clock Module Operation 4.2.6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy, reducing electromagnetic interference (EMI) frequencies across 32 DCOCLK clock cycles. The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate.
Page 118: Disabling The Fll Hardware And Modulator
4.2.7 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCG0 = 1. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized. The DCO modulator is disabled when SCFQ_M = 1. When the DCO modulator is disabled, the DCOCLK is adjusted to the nearest of the available DCO taps.
Page 119: Fll+ Fail-Safe Operation
Buffered Clock Output 4.2.10 FLL+ Fail-Safe Operation The FLL+ module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 4−4. The available fault conditions are: Low-frequency oscillator fault (LFOF) for LFXT1 in LF mode High-frequency oscillator fault (XT1OF) for LFXT1 in HF mode High-frequency oscillator fault (XT2OF) for XT2 DCO fault flag (DCOF) for the DCO...
Page 120: Fll+ Clock Module Registers
4.3 FLL+ Clock Module Registers The FLL+ registers are listed in Table 4−2. Table 4−2. FLL+ Registers Register System clock control System clock frequency integrator 0 System clock frequency integrator 1 FLL+ control register 0 FLL+ control register 1 SFR interrupt enable register 1 SFR interrupt flag register 1 FLL+ Clock Module Registers Short Form...
Page 121 FLL+ Clock Module Registers SCFQCTL, System Clock Control Register SCFQ_M rw−0 rw−0 rw−0 SCFQ_M Bit 7 Modulation. This enables or disables modulation Modulation enabled Modulation disabled Bits Multiplier. These bits set the multiplier value for the DCO. N must be > 0 or unpredictable operation will result.
Page 122 SCFI1, System Clock Frequency Integrator Register 1 DCOx rw−0 rw−0 rw−0 DCOx Bits These bits select the DCO tap and are modified automatically by the FLL+. MODx Bit 2 Most significant modulator bits. Bit 2 is the modulator MSB. These bits af- fect the modulator pattern.
Page 123 FLL+ Clock Module Registers FLL_CTL0, FLL+ Control Register 0 DCOPLUS XTS_FLL XCAPxPF rw−0 rw−0 rw−0 † Not present in MSP430x41x, MSP430x42x devices DCOPLUS Bit 7 DCO output pre-divider. This bit selects if the DCO output is pre-divided before sourcing MCLK or SMCLK. The division rate is selected with the FLL_DIV bits DCO output is divided DCO output is not divided...
Page 124 FLL_CTL1, FLL+ Control Register 1 SMCLK † Unused XT2OFF † rw−(1) † Not present in MSP430x41x, MSP430x42x devices. Unused Bit 7 SMCLKOFF Bit 6 SMCLK off. This bit turns off SMCLK. Not present in MSP430x41x, MSPx42x devices. SMCLK is on SMCLK is off XT2OFF Bit 5...
Page 125 FLL+ Clock Module Registers IE1, Interrupt Enable Register 1 Bits These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 126: Flash Memory Controller
Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller. Topic Flash Memory Introduction ........Flash Memory Segmentation .
Page 127 Flash Memory Introduction 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three registers, a timing generator, and a voltage generator to supply program and erase voltages.
Page 128 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections.
Page 129: Flash Memory Operation
Flash Memory Operation 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage.
Page 130: Erasing Flash Memory
5.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 5−1.
Page 131 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes.
Page 132 Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again.
Page 133: Writing Flash Memory
Flash Memory Operation 5.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 5−1. Interrupts are automatically disabled during a flash write and re-enabled after the write. Any interrupt that occurred during the write will have its associated flag set, and will generate an interrupt request when re-enabled.
Page 134 In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 32 of the 35 f cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates.
Page 135 Flash Memory Operation Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5−9. Figure 5−9. Initiating a Byte/Word Write from RAM Disable watchdog Setup flash controller and set WRT=1 Write byte or word Set WRT=0, LOCK = 1 re-enable watchdog ;...
Page 136 Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time t a block write.
Page 137 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 5−8 and the following example. Figure 5−11. Block Write Flow Disable watchdog Setup flash controller Set BLKWRT=WRT=1 Write byte or word Set BLKWRT=0 Set WRT=0, LOCK=1 re-enable WDT 5-12 Flash Memory Controller...
Page 138 ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. #32,R5 #0F000h,R6 #WDTPW+WDTHOLD,&WDTCTL L1 BIT #BUSY,&FCTL3 #FWKEY+FSSEL1+FN0,&FCTL2 ;...
Page 139: Flash Memory Access During Write Or Erase
Flash Memory Operation 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
Page 140: Stopping A Write Or Erase Cycle
5.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset.
Page 141 Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals (5 signals on 20- and 28-pin devices), ground and optionally V The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible.
Page 142: Flash Memory Registers
5.4 Flash Memory Registers The flash memory registers are listed in Table 5−4. Table 5−4. Flash Memory Registers Register Flash memory control register 1 Flash memory control register 2 Flash memory control register 3 Interrupt Enable 1 Short Form Register Type Address FCTL1 Read/write 0128h...
Page 143 Flash Memory Registers FCTL1, Flash Memory Control Register FWKEY, Must be written as 0A5h BLKWRT Reserved rw−0 rw−0 FRKEY/ Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC FWKEY 15-8 will be generated. BLKWRT Bit 7 Block write mode.
Page 144 FCTL2, Flash Memory Control Register FSSELx rw−0 rw−1 rw-0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated. FSSELx Bits Flash controller clock source select 7−6 ACLK MCLK SMCLK SMCLK Bits Flash controller clock divider.
Page 145 Flash Memory Registers FCTL3, Flash Memory Control Register FCTL3 Reserved Reserved EMEX rw-0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated. Reserved Bits Reserved. Always read as 0. EMEX Bit 5 Emergency exit...
Page 146 IE1, Interrupt Enable Register 1 ACCVIE rw−0 Bits These bits may be used by other modules. See device-specific datasheet. 7-6, ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 147: Supply Voltage Supervisor
Supply Voltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented in all MSP430x4x devices. Topic SVS Introduction ..........SVS Operation .
Page 148: Svs Introduction
SVS Introduction 6.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the AV voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
Page 149 Figure 6−1. SVS Block Diagram SVSIN 1111 1101 − 1100 0011 0010 1.25V 0001 Brownout Reset ~ 50us t Reset ~ 50us PORON SVSON SVSOP Supply Voltage Supervisor SVS Introduction SVS_POR SVSOUT Set SVSFG Reset SVSFG SVSCTL Bits...
Page 150: Svs Operation
SVS Operation 6.2 SVS Operation The SVS detects if the AV configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 6.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V VLDx = 0 and on when VLDx >...
Page 151: Changing The Vldx Bits
6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented to allows the SVS circuitry to settle. During each delay, the SVS will not set SVSFG. The delays, t delay takes affect when VLDx is changed from zero to any non-zero d(SVSon) value and is a approximately 50 s.
Page 152: Svs Operating Range
SVS Operation 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AV SVS/Brownout interoperation are shown in Figure 6−3. Figure 6−3. Operating Levels for SVS and Brownout/Reset Circuit V hys(SVS_IT−) V (SVS_IT−) V (SVSstart) hys(B_IT−) V (B_IT−)
Page 153: Svs Registers
6.3 SVS Registers The SVS registers are listed in Table 6−1. Table 6−1. SVS Registers Register SVS Control Register SVSCTL, SVS Control Register VLDx † † † rw−0 rw−0 rw−0 † Reset by a brownout reset only, not by a POR or PUC. VLDx Bits Voltage level detect.
Page 154: Hardware Multiplier
Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier is implemented in MSP430x44x devices. Topic Hardware Multiplier Introduction Hardware Multiplier Operation ........Hardware Multiplier Registers .
Page 155: Hardware Multiplier Introduction
Hardware Multiplier Introduction 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Page 156: Hardware Multiplier Operation
7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT.
Page 157: Result Registers
Hardware Multiplier Operation 7.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 7−2. Table 7−2. RESHI Contents Mode MPYS MACS...
Page 158: Software Examples
7.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. ; 16x16 Unsigned Multiply ;...
Page 159: Indirect Addressing Of Reslo
Hardware Multiplier Operation 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers: ; Access multiplier results with indirect addressing 7.2.5 Using Interrupts If an interrupt occurs after writing OP1, but before writing OP2, and the...
Page 160: Hardware Multiplier Registers
7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7−4. Table 7−4. Hardware Multiplier Registers Register Operand one - multiply Operand one - signed multiply Operand one - multiply accumulate Operand one - signed multiply accumulate MACS Operand two Result low word Result high word...
Page 161: Dma Controller
The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. The DMA controller is implemented in MSP430FG43x and implements only one DMA channel. Topic DMA Introduction ..........DMA Operation .
Page 162: Dma Introduction
8.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. MSP430FG43x devices implement only one DMA channel. Therefore some features described in this chapter are not applicable to MSP430FG43x devices.
Page 163 Figure 8−1. DMA Controller Block Diagram DMA0TSELx Halt DMAREQ 0000 TACCR2_CCIFG 0001 TBCCR2_CCIFG 0010 USART0 data received 0011 USART0 transmit ready 0100 DAC12_0IFG 0101 0110 ADC12IFGx 0111 TACCR0_CCIFG TBCCR0_CCIFG 1000 USART1 data received 1001 USART1 transmit ready 1010 Multiplier ready 1011 No trigger −−−...
Page 164: Dma Operation
8.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses.
Page 165: Dma Transfer Modes
8.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 8−1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode.
Page 166 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 8−3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer.
Page 167 Figure 8−3. DMA Single Transfer State Diagram DMAEN = 0 Reset DMAEN = 0 DMAEN = 0 DMAEN = 1 DMAREQ = 0 T_Size DMAxSZ DMAxSZ T_Size DMAxSA T_SourceAdd [ DMADTx = 0 DMAxDA T_DestAdd AND DMAxSZ = 0] OR DMAEN = 0 DMAABORT = 1 Idle DMAREQ = 0...
Page 168 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered.
Page 169 Figure 8−4. DMA Block Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size DMAxSZ DMAxSZ [DMADTx = 1 DMAxSA AND DMAxSZ = 0] DMAxDA DMAEN = 0 DMAABORT = 1 DMAABORT=0 Wait for Trigger 2 x MCLK Hold CPU, Transfer one word/byte...
Page 170 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
Page 171 Figure 8−5. DMA Burst-Block Transfer State Diagram DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size DMAxSZ DMAxSZ [DMADTx = {2, 3} DMAxSA AND DMAxSZ = 0] DMAxDA DMAEN = 0 DMAABORT = 1 DMAABORT=0 Wait for Trigger 2 x MCLK Hold CPU, Transfer one word/byte...
Page 172: Initiating Dma Transfers
8.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place.
Page 173 Table 8−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts.
Page 174: Stopping Dma Transfers
8.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. A burst-block transfer may be stopped by clearing the DMAEN bit. 8.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0−DMA1−DMA2.
Page 175: Dma Transfer Cycle Time
8.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup.
Page 176: Using Dma With System Interrupts
8.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine.
Page 177: Using Adc12 With The Dma Controller
8.2.9 Using the I C Module with the DMA Controller The I C module provides two trigger sources for the DMA controller. The I module can trigger a transfer when new I transmit data is needed. The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the I be used to transfer data from the I data.
Page 178: Dma Registers
8.3 DMA Registers The DMA registers are listed in Table 8−4. Table 8−4. DMA Registers Register DMA control 0 DMA control 1 DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address...
Page 179 DMACTL0, DMA Control Register 0 Reserved rw−(0) rw−(0) rw−(0) DMA1TSELx rw−(0) rw−(0) rw−(0) Reserved Bits Reserved 15−12 DMA2 Bits DMA trigger select. These bits select the DMA transfer trigger. TSELx 11−8 0000 DMAREQ bit (software trigger) 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFG0 (UART/SPI mode), USART0 data received (I 0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I...
Page 180 DMACTL1, DMA Control Register 1 Reserved Bits Reserved. Read only. Always read as 0. 15−3 Bit 2 DMA on fetch ONFETCH The DMA transfer occurs immediately The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin.
Page 181 DMAxCTL, DMA Channel x Control Register Reserved DMADTx rw−(0) rw−(0) rw−(0) DMALEVEL DSTBYTE SRCBYTE rw−(0) rw−(0) rw−(0) Reserved Bit 15 Reserved DMADTx Bits DMA Transfer mode. 14−12 000 Single transfer 001 Block transfer 010 Burst-block transfer 011 Burst-block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst-block transfer 111 Repeated burst-block transfer...
Page 182 Bit 6 DMA source byte. This bit selects the source as a byte or word. SRCBYTE Word Byte Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive LEVEL triggers. Edge sensitive (rising edge) Level sensitive (high level) DMAEN Bit 4 DMA enable Disabled...
Page 183 DMAxDA, DMA Destination Address Register DMAxDAx Bits DMA destination address. The destination address register points to the 15−0 destination address for single transfers or the first address for block transfers. The DMAxDA register remains unchanged during block and burst-block transfers. DMAxSZ, DMA Size Address Register DMAxSZx Bits...
Page 184: Digital I/O
This chapter describes the operation of the digital I/O ports. Ports P1-P6 are implemented in all MSP430x4xx devices. Topic Digital I/O Introduction ........
Page 185: Digital I/O Introduction
Digital I/O Introduction 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability.
Page 186: Digital I/O Operation
9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. 9.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function.
Page 187: Function Select Registers Pxsel
Digital I/O Operation 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function − I/O port or peripheral module function. Bit = 0: I/O Function is selected for the pin Bit = 1: Peripheral module function is selected for the pin Setting PxSELx = 1 does not automatically set the pin direction.
Page 188: P1 And P2 Interrupts
9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.
Page 189: Configuring Unused Port Pins
Digital I/O Operation Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags.
Page 190: Digital I/O Registers
9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6. The digital I/O registers are listed in Table 9−1. Table 9−1. Digital I/O Registers Port Register Short Form P1IN Input P1OUT...
Page 191: Watchdog Timer, Watchdog Timer+
The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the watchdog timer. The watchdog timer is implemented in all MSP430x4xx devices, except those with the enhanced watchdog timer, WDT+. The WDT+ is implemented in the MSP430x42x, MSP430FE42x, and MSP430F42x0 devices.
Page 192: Watchdog Timer Introduction
Watchdog Timer Introduction 10.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
Page 193 Figure 10−1. Watchdog Timer Block Diagram WDTQn Int. Flag Pulse Generator † MCLK SMCLK ACLK †MSP430x42x and MSP430FE42x devices only 16−bit Password Counter Compare Clear (Asyn) Fail-Safe † Logic WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 Clock Request † Logic Watchdog Timer, Watchdog Timer+ Watchdog Timer Introduction...
Page 194: Watchdog Timer Operation
Watchdog Timer Operation 10.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register.
Page 195: Watchdog Timer Interrupts
10.2.4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control. The WDT interrupt flag, WDTIFG, located in IFG1.0 The WDT interrupt enable, WDTIE, located in IE1.0 When using the WDT in the watchdog mode, the WDTIFG flag sources a reset vector interrupt.
Page 196: Operation In Low-Power Modes
Watchdog Timer Operation 10.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured.
Page 197: Watchdog Timer Registers
10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10−1. Table 10−1.Watchdog Timer Registers Register Watchdog timer control register SFR interrupt enable register 1 SFR interrupt flag register 1 † WDTIFG is reset with POR Short Form Register Type Address WDTCTL Read/write...
Page 198 Watchdog Timer Registers WDTCTL, Watchdog Timer Register WDTPW, must be written as 05Ah WDTHOLD WDTNMIES WDTNMI rw−0 rw−0 rw−0 WDTPW Bits Watchdog timer password. Always read as 069h. Must be written as 05Ah, or 15-8 a PUC will be generated. WDTHOLD Bit 7 Watchdog timer hold.
Page 199 IE1, Interrupt Enable Register 1 Bits These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 200 Watchdog Timer Registers IFG1, Interrupt Flag Register 1 Bits These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 201: Basic Timer1
The Basic Timer1 module is two independent, cascadable 8-bit timers. This chapter describes the Basic Timer1. Basic Timer1 is implemented in all MSP430x4xx devices. Topic 11.1 Basic Timer1 Introduction ........
Page 202: Basic Timer1 Introduction
Basic Timer1 Introduction 11.1 Basic Timer1 Introduction The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function. Some uses for the Basic Timer1 include: Real-time clock (RTC) function Software time increments Basic Timer1 features include:...
Page 203 Figure 11−1. Basic Timer1 Block Diagram BTDIV BTHOLD ACLK BTSSEL ACLK:256 SMCLK Basic Timer1 Introduction BTCNT1 BTFRFQx CLK1 Q4 Q5 Q6 Q7 BTCNT2 CLK2 Q4 Q5 Q6 Q7 Basic Timer1 f LCD BTIPx Set_BTIFG 11-3...
Page 204: Basic Timer1 Operation
Basic Timer1 Introduction 11.2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8-bit timers or one 16-bit timer with the BTCTL register. The BTCTL register is an 8-bit, read/write register. Any read or write access must use byte instructions. The Basic Timer1 controls the LCD frame frequency with BTCNT1.
Page 205: Basic Timer1 Interrupts
11.2.4 Basic Timer1 Operation: Signal f The LCD controller (but not the LCDA controller) uses the f BTCNT1 to generate the timing for common and segment lines. ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating f frequency is selected with the BTFRFQx bits and can by ACLK/256, ACLK/128, ACLK/64, or ACLK/32.
Page 206: Basic Timer1 Registers
Basic Timer1 Introduction 11.3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 11−1. Table 11−1. Basic Timer1 Registers Register Basic Timer1 Control Basic Timer1 Counter 1 Basic Timer1 Counter 2 SFR interrupt flag register 2 SFR interrupt enable register 2 Note: The Basic Timer1 registers should be configured at power-up.
Page 207 BTCTL, Basic Timer1 Control Register BTSSEL BTHOLD BTDIV BTSSEL Bit 7 BTCNT2 clock select. This bit, together with the BTDIV bit, selects the clock source for BTCNT2. See the description for BTDIV. BTHOLD Bit 6 Basic Timer1 Hold. BTCNT1 and BTCNT2 are operational BTCNT1 is held if BTDIV=1 BTCNT2 is held BTDIV...
Page 208 Basic Timer1 Introduction BTCNT1, Basic Timer1 Counter 1 BTCNT1x Bits BTCNT1 register. The BTCNT1 register is the count of BTCNT1. 7−0 BTCNT2, Basic Timer1 Counter 2 BTCNT2x Bits BTCNT2 register. The BTCNT2 register is the count of BTCNT2. 7−0 11-8 Basic Timer1 BTCNT1x BTCNT2x...
Page 209 IE2, Interrupt Enable Register 2 BTIE rw−0 BTIE Bit 7 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 210: Timer_A
Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_A. Timer_A3 (three capture/compare registers) is implemented in all MSP430x4xx devices. Timer1_A5 (five capture/compare registers) is also implemented on MSP430x415, MSP430x417, and MSP430xW42x devices. Topic 12.1 Timer_A Introduction .
Page 211: Timer_A Introduction
Timer_A Introduction 12.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three or five capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 212 Figure 12−1. Timer_A Block Diagram Timer Clock TASSELx TACLK Divider 1/2/4/8 ACLK SMCLK CCISx CCI4A Capture Mode CCI4B Timer Clock SCCI Output Unit4 EQU0 OUTMODx 16−bit Timer Clear TACLR logic TACCR4 Sync Compararator 2 EQU4 D Set Q Timer Clock Reset Timer_A Introduction Timer Block...
Page 213: Timer_A Operation
Timer_A Operation 12.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software.
Page 214: Starting The Timer
12.2.2 Starting the Timer The timer may be started, or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0.
Page 215 Timer_A Operation Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 12−2. The number of timer counts in the period is TACCR0+1.
Page 216 Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 12−4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. Figure 12−4. Continuous Mode 0FFFFh The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.
Page 217 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine.
Page 218 Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 12−7.
Page 219 Timer_A Operation Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The new period takes affect after the counter counts down to zero. When the timer is counting in the up direction, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down.
Page 220: Capture/Compare Blocks
The timer value is copied into the TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB.
Page 221 Timer_A Operation Figure 12−11.Capture Cycle Capture Taken Clear Bit COV in Register TACCTLx Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between V changes state: Compare Mode...
Page 222: Output Unit
12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12−2.
Page 223 Timer_A Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 12−12 using TACCR0 and TACCR1. Figure 12−12.
Page 224 Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 12−13 using TACCR0 and TACCR1. Figure 12−13. Output Example—Timer in Continuous Mode 0FFFFh TACCR0 TACCR1...
Page 225 Timer_A Operation Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 12−14 using TACCR0 and TACCR2. Figure 12−14.
Page 226: Timer_A Interrupts
12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: TACCR0 interrupt vector for TACCR0 CCIFG TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register.
Page 227 Timer_A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 228: Timer_A Registers
12.3 Timer_A Registers The Timer_A registers are listed in Table 12−3 and Table 12−4. Table 12−3.Timer_A3 Registers Register Timer_A control Timer0_A3 Control Timer_A counter Timer0_A3 counter Timer_A capture/compare control 0 Timer0_A3 capture/compare control 0 Timer_A capture/compare 0 Timer0_A3 capture/compare 0 Timer_A capture/compare control 1 Timer0_A3 capture/compare control 1 Timer_A capture/compare 1...
Page 229 Timer_A Registers TACTL, Timer_A Control Register Unused rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits Unused 15-10 TASSELx Bits Timer_A clock source select TACLK ACLK SMCLK Inverted TACLK Bits Input divider. These bits select the divider for the input clock. Bits Mode control.
Page 230 TAR, Timer_A Register rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Bits Timer_A register. The TAR register is the count of Timer_A. TARx 15-0 TARx rw−(0) rw−(0) rw−(0) TARx rw−(0) rw−(0) rw−(0) Timer_A Registers rw−(0) rw−(0) rw−(0) rw−(0) Timer_A 12-21...
Page 231 Timer_A Registers TACCTLx, Capture/Compare Control Register CCISx rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select. These bits select the TACCRx input signal. 13-12 See the device-specific datasheet for specific signal connections.
Page 232 CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 233: Timer_B
Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_B. Timer_B3 (three capture/compare registers) is implemented in MSP430x43x devices. Timer_B7 (seven capture/compare registers) is implemented in MSP430x44x. Topic 13.1 Timer_B Introduction ......... 13.2 Timer_B Operation .
Page 234: Timer_B Introduction
Timer_B Introduction 13.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 235 Figure 13−1. Timer_B Block Diagram Timer Clock TBSSELx TBCLK Divider 1/2/4/8 ACLK SMCLK TBCLGRPx Group Load Logic CCISx CCI6A Capture Mode CCI6B Timer Clock CLLDx TBR=0 CCR5 EQU0 CCR4 UP/DOWN CCR1 Output Unit6 EQU0 OUTMODx 16−bit Timer Clear 10 12 16 TBCLR logic TBCCR6...
Page 236: Timer_B Operation
Timer_B Operation 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 13.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software.
Page 237: Timer Mode Control
13.2.2 Starting the Timer The timer may be started or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0.
Page 238 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 13−2. The number of timer counts in the period is TBCL0+1.
Page 239 Continuous Mode In continuous mode the timer repeatedly counts up to TBR from zero as shown in Figure 13−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 13−4. Continuous Mode TBR (max) The TBIFG interrupt flag is set when the timer counts from TBR Figure 13−5 shows the flag set cycle.
Page 240 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
Page 241 Up/Down Mode The up/down mode is used if the timer period must be different from TBR counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 13−7.
Page 242 Timer_B Operation Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero.
Page 243: Capture/Compare Blocks
The timer value is copied into the TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB.
Page 244 Timer_B Operation Figure 13−11.Capture Cycle Capture Taken Clear Bit COV in Register TBCCTLx Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets bit CCIS1=1 and toggles bit CCIS0 to switch the capture signal between V CCIS0 changes state: Compare Mode...
Page 245 Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx.
Page 246: Output Unit
Timer_B Operation 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a high-impedance state.
Page 247 Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 13−12 using TBCL0 and TBCL1. Figure 13−12.
Page 248 Timer_B Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 13−13 using TBCL0 and TBCL1. Figure 13−13. Output Example—Timer in Continuous Mode TBR (max) TBCL0 TBCL1...
Page 249 Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 13−14 using TBCL0 and TBCL3. Figure 13−14.
Page 250: Timer_B Interrupts
Timer_B Operation 13.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: TBCCR0 interrupt vector for TBCCR0 CCIFG TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register.
Page 251 TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction.
Page 252: Timer_B Registers
Timer_B Registers 13.3 Timer_B Registers The Timer_B registers are listed in Table 13−5. Table 13−5.Timer_B Registers Register Timer_B control Timer_B counter Timer_B capture/compare control 0 Timer_B capture/compare 0 Timer_B capture/compare control 1 Timer_B capture/compare 1 Timer_B capture/compare control 2 Timer_B capture/compare 2 Timer_B capture/compare control 3 Timer_B capture/compare 3 Timer_B capture/compare control 4...
Page 253 Timer_B Control Register TBCTL Unused TBCLGRPx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bit 15 Unused TBCLGRP TBCLx group 14-13 Each TBCLx latch loads independently TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
Page 254 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request. Interrupt disabled Interrupt enabled TBIFG...
Page 255 TBCCTLx, Capture/Compare Control Register CCISx rw−(0) rw−(0) rw−(0) OUTMODx rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select. These bits select the TBCCRx input signal. 13-12 See the device-specific datasheet for specific signal connections.
Page 256 Timer_B Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 257 TBIV, Timer_B Interrupt Vector Register Bits Timer_B interrupt vector value TBIVx 15-0 TBIV Contents † MSP430x4xx, devices only TBIVx r−(0) r−(0) r−(0) Interrupt Source Interrupt Flag No interrupt pending − Capture/compare 1 TBCCR1 CCIFG Capture/compare 2 TBCCR2 CCIFG † Capture/compare 3 TBCCR3 CCIFG †...
Page 258: Usart Peripheral Interface, Uart Mode
USART Peripheral Interface, UART Mode universal synchronous/asynchronous peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1.
Page 259: Usart Introduction: Uart Mode
USART Introduction: UART Mode 14.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include: 7- or 8-bit data with odd, even, or non-parity Independent transmit and receive shift registers Separate transmit and receive buffer registers...
Page 260 Figure 14−1. USART Block Diagram: UART Mode SWRST URXEx* URXEIE URXWIE Receive Control Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 CHAR Baud−Rate Generator UCLKI ACLK Prescaler/Divider UxBRx SMCLK SMCLK Modulator UxMCTL CHAR Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF UTXIFGx*...
Page 261: Usart Operation: Uart Mode
USART Operation: UART Mode 14.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency.
Page 262: Asynchronous Communication Formats
14.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 14−3.
Page 263 USART Operation: UART Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag.
Page 264 Address Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 14−4. The first character in a block of characters carries a set address bit which indicates that the character is an address.
Page 265 USART Operation: UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t (approximately 300 ns) will be ignored. See the device-specific datasheet for parameters. When a low period on URXDx exceeds t a majority vote is taken for the start bit.
Page 266: Usart Receive Enable
14.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 14−5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF, contains the character moved from the RX shift register after the character is received.
Page 267: Usart Transmit Enable
USART Operation: UART Mode 14.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins.
Page 268: Uart Baud Rate Generation
14.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 14−7. This combination supports fractional divisors for baud rate generation. The maximum USART baud rate is one-third the UART source clock frequency BRCLK.
Page 269 USART Operation: UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs.
Page 270 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by: Error [%] + baud rate With: baud rate: Desired baud rate BRCLK: UxBR:...
Page 271 USART Operation: UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 14−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.
Page 272 For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7=0, m6=1, m5=1, m4=0, m3=1, m2=0, m1=1 and m0=1 The LSB of UxMCTL is used first.
Page 273 USART Operation: UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 14−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit.
Page 274: Usart Interrupts
14.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 275 USART Operation: UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 276 Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation. The ultra-fast turn-on of the DCO allows character reception after the start edge detection.
Page 277 USART Operation: UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t (approximately 300 ns) will be ignored by the USART and no interrupt request will be generated as shown in Figure 14−12.
Page 278: Usart Registers: Uart Mode
14.3 USART Registers: UART Mode Table 14−3 lists the registers for all devices implementing a USART module. Table 14−4 applies only to devices with a second USART module, USART1. Table 14−3.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0...
Page 279 USART Registers: UART Mode UxCTL, USART Control Register PENA rw−0 rw−0 rw−0 PENA Bit 7 Parity enable Parity disabled. Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Bit 6 Parity select.
Page 280 UxTCTL, USART Transmit Control Register Unused CKPL SSELx rw−0 rw−0 rw−0 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select UCLKI = UCLK UCLKI = inverted UCLK SSELx Bits Source select. These bits select the BRCLK source clock. UCLKI ACLK SMCLK SMCLK...
Page 281 USART Registers: UART Mode UxRCTL, USART Receive Control Register rw−0 rw−0 rw−0 Bit 7 Framing error flag No error Character received with low stop bit Bit 6 Parity error flag. When PENA = 0, PE is read as 0. No error Character received with parity error Bit 5 Overrun error flag.
Page 282 UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 UxBRx The valid baud-rate control range is 3 {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR <3. UxMCTL, USART Modulation Control Register UxMCTLx Bits Modulation bits. These bits select the modulation for BRCLK. 7−0 USART Registers: UART Mode UxBR...
Page 283 USART Registers: UART Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 284 ME1, Module Enable Register 1 UTXE0 URXE0 rw−0 rw−0 UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0. Module not enabled Module enabled URXE0 Bit 6 USART0 receive enable. This bit enables the receiver for USART0. Module not enabled Module enabled Bits...
Page 285 USART Registers: UART Mode IE1, Interrupt Enable Register 1 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 286 IFG1, Interrupt Flag Register 1 UTXIFG0 URXIFG0 rw−1 rw−0 † UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending † URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 287: Usart Peripheral Interface, Spi Mode
USART Peripheral Interface, SPI Mode universal synchronous/asynchronous peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1.
Page 288: Usart Introduction: Spi Mode
USART Introduction: SPI Mode 15.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include: 7- or 8-bit data length 3-pin and 4-pin SPI operation...
Page 289 Figure 15−1. USART Block Diagram: SPI Mode SWRST USPIEx* URXEIE URXWIE Receive Control Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 CHAR Baud−Rate Generator UCLKI ACLK Prescaler/Divider UxBRx SMCLK SMCLK Modulator UxMCTL CHAR Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF UTXIFGx*...
Page 290: Usart Operation: Spi Mode
USART Operation: SPI Mode 15.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: SIMO SOMI...
Page 291: Master Mode
15.2.2 Master Mode Figure 15−2. USART Master and External Slave MASTER Receive Buffer UxRXBUF Transmit Buffer UxTXBUF Receive Shift Register Transmit Shift Register MSP430 USART Figure 15−2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates data transfer when data is moved to the transmit data buffer UxTXBUF.
Page 292: Slave Mode
USART Operation: SPI Mode 15.2.3 Slave Mode Figure 15−3. USART Slave and External Master MASTER SIMO SPI Receive Buffer Px.x SOMI Data Shift Register DSR SCLK COMMON SPI Figure 15−3 shows the USART as a slave in both 3-pin and 4-pin configurations.
Page 293: Spi Enable
15.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated.
Page 294 USART Operation: SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 15−6 and Figure 15−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. Figure 15−6. SPI Master Receive-Enable State Diagram USPIEx = 0 USPIEx = 1 Receive...
Page 295: Serial Clock Control
15.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 15−8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are don’t care.
Page 296 USART Operation: SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 15−9. Figure 15−9. USART SPI Timing Cycle# CKPH CKPL UCLK...
Page 297: Spi Interrupts
15.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 298 USART Operation: SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 15−11 and Figure 15−12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 299: Usart Registers: Spi Mode
15.3 USART Registers: SPI Mode Table 15−1 lists the registers for all devices implementing a USART module. Table 15−2 applies only to devices with a second USART module, USART1. Table 15−1.USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0...
Page 300 USART Registers: SPI Mode UxCTL, USART Control Register † Unused Unused rw−0 rw−0 rw−0 Unused Bits Unused 7−6 † Bit 5 I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. SPI mode C mode CHAR Bit 4 Character length 7-bit data...
Page 301 UxTCTL, USART Transmit Control Register CKPH CKPL SSELx rw−0 rw−0 rw−0 CKPH Bit 7 Clock phase select. Controls the phase of UCLK. Normal UCLK clocking scheme UCLK is delayed by one half cycle CKPL Bit 6 Clock polarity select The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK.
Page 302 USART Registers: SPI Mode UxRCTL, USART Receive Control Register Unused rw−0 rw−0 rw−0 Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. No conflict detected A negative edge occurred on STE, indicating bus conflict Undefined Bit 6...
Page 303 UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. UxMCTL, USART Modulation Control Register UxMCTLx Bits The modulation control register is not used for SPI mode and should be set...
Page 304 USART Registers: SPI Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 305 ME1, Module Enable Register 1 USPIE0 rw−0 Bit 7 This bit may be used by other modules. See device-specific datasheet. USPIE0 Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0. Module not enabled Module enabled Bits These bits may be used by other modules.
Page 306 USART Registers: SPI Mode IE1, Interrupt Enable Register 1 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 307 IFG1, Interrupt Flag Register 1 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 308 The OA is a general purpose operational amplifier. This chapter describes the OA. Three OA modules are implemented in the MSP430FG43x devices. Topic 16.1 OA Introduction ..........16.2 OA Operation .
Page 309: Oa Introduction
OA Introduction 16.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analog- to-digital conversion. Features of the OA include: Single supply, low-current operation Rail-to-rail output Software selectable Rail-to-Rail input Programmable settling time vs. power consumption Software selectable configurations Software selectable feedback resistor ladder for PGA implementations Note: Multiple OA Modules...
Page 310 Figure 16−1. OA Block Diagram OAPx=3 OAFCx=6 OANx=3 OAPx OAxI0 OA0I1 Int. DAC12_0OUT Int. DAC12_1OUT OA1TAP (OA0) OA2TAP (OA1) OA0TAP (OA2) OANx OAxI0 OAxI1 Int. DAC12_0OUT Int. DAC12_1OUT BOTTOM OAFCx=1 OAFCx={2 − 7} OAxTAP OAADC0 A12 ext. (OA0) A13 ext. (OA1) A14 ext.
Page 311: Oa Operation
16.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. 16.2.1 OA Amplifier The OA is a configurable, low-current, rail-to-rail operational amplifier. It can be configured as an inverting amplifier, or a non-inverting amplifier, or can be combined with other OA modules to form differential amplifiers.
Page 312: Oa Configurations
16.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits. as listed in Table 16−1. Table 16−1.OA Mode Select OAFCx General Purpose Opamp Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAxCTL0 bits define the signal routing.
Page 313 Non-Inverting PGA Mode In this mode the output of the OAx is connected to R connected to AV the OAx providing a non-inverting amplifier configuration with a programmable gain of [1+OAxTAP ratio]. The OAxTAP ratio is selected by the OAFBRx bits. If the OAFBRx bits = 0, the gain is unity.
Page 314 Figure 16−2 shows an example of a two-opamp differential amplifier using OA0 and OA1. The control register settings and are shown in Table 16−2. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 16−3.
Page 315 Figure 16−3. Two Opamp Differential Amplifier OAx Interconnections OAPx OAPx OAPMx − 16-8 OAADC0 A13 ext. OAPMx OAADC1 − OAADC1 OAFBRx OA1R BOTTOM OA0OUT A13 int. A3 int./ext., OA1O...
Page 316 Figure 16−4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2. The control register settings are shown in Table 16−4. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal.
Page 317 Figure 16−5. Three Opamp Differential Amplifier OAx Interconnections OAPx OAPMx OA0OUT − OAFBRx OA0TAP OA0R BOTTOM OAPx OAPMx − 16-10 A14 ext. OAPMx − OA0TAP OAADC1 OAFBRx OA2R BOTTOM OA1OUT OAADC0 A14 int. OAADC1 A5 int./ext., OA2O...
Page 318: Oa Registers
16.3 OA Registers The OA registers are listed in Table 16−6. Table 16−6. Register OA0 Control Register 0 OA0 Control Register 1 OA1 Control Register 0 OA1 Control Register 1 OA2 Control Register 0 OA2 Control Register 1 Short Form Register Type Address OA0CTL0 Read/write...
Page 319 OA Registers OAxCTL0, Opamp Control Register 0 OANx OAPx rw−0 rw−0 rw−0 OANx Bits Inverting input select. These bits select the input signal for the OA inverting input. OAxI0 OAxI1 DAC0 internal DAC1 internal OAPx Bits Non-inverting input select. These bits select the input signal for the OA non-inverting input.
Page 320 OAxCTL1, Opamp Control Register 1 OAFBRx rw−0 rw−0 rw−0 OAFBRx Bits OAx feedback resistor select 000 Tap 0 001 Tap 1 010 Tap 2 011 Tap 3 100 Tap 4 101 Tap 5 110 Tap 6 111 Tap 7 OAFCx Bits OAx function control.
Page 321: Comparator_A
Comparator_A is an analog voltage comparator. This chapter describes Comparator_A. Comparator_A is implemented in all MSP430x4xx devices. Topic 17.1 Comparator_A Introduction ........
Page 322: Comparator_A Introduction
Comparator_A Introduction 17.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A include: Inverting and non-inverting terminal input multiplexer Software selectable RC-filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator...
Page 323 Figure 17−1. Comparator_A Block Diagram CAEX P2CA0 − − P2CA1 CAREFx CARSEL V CAREF CAON Tau ~ 2.0ms 0.5x 0.25x Comparator_A Introduction CCI1B CAOUT Set_CAIFG Comparator_A 17-3...
Page 324: Comparator_A Operation
Comparator_A Operation 17.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 17.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the –...
Page 325: Output Filter
17.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small.
Page 326: Comparator_A, Port Disable Register Capd
Comparator_A Operation 17.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from V parasitic current occurs if the input voltage is near the transition level of the gate.
Page 327: Comparator_A Used To Measure Resistive Elements
17.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 17−5.
Page 328 Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 17−6. Figure 17−6. Timing for Temperature Measurement Systems 0.25 Phase I: Charge The V voltage conversion, but are not critical since they cancel in the ratio: –R meas...
Page 329: Comparator_A Registers
17.3 Comparator_A Registers The Comparator_A registers are listed in Table 17−1. Table 17−1.Comparator_A Registers Register Comparator_A control register 1 Comparator_A control register 2 Comparator_A port disable Short Form Register Type Address CACTL1 Read/write 059h CACTL2 Read/write 05Ah CAPD Read/write 05Bh Comparator_A Registers Initial State Reset with POR...
Page 330 Comparator_A Registers CACTL1, Comparator_A Control Register 1 CAEX CARSEL CAREFx rw−(0) rw−(0) rw−(0) CAEX Bit 7 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. CARSEL Bit 6 Comparator_A reference select. This bit selects which terminal the V is applied to.
Page 331 CACTL2, Comparator_A Control Register 2 Unused rw−(0) rw−(0) rw−(0) Bits Unused. Unused Bit 3 Pin to CA1. This bit selects the CA1 pin function. P2CA1 The pin is not connected to CA1 The pin is connected to CA1 Bit 2 Pin to CA0.
Page 332: Lcd Controller
The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes LCD controller. The LCD controller is implemented on all MSP430x4xx devices, except the MSP430x42x0 devices. Topic 18.1 LCD Controller Introduction ........
Page 333: Lcd Controller Introduction
LCD Controller Introduction 18.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: Display memory Automatic signal generation Configurable frame frequency...
Page 334 Figure 18−1. LCD Controller Block Diagram 0A4h Display Memory 8−bits 091h LCDP2 LCDP1 LCDP0 LCDMX1 LCDMX0 LCDSON LCDON f LCD Timing Generator (from Basic Timer) OSCOFF (from SR) LCD Controller Introduction SEG39 SEG38 Segment Output Control SEG1 SEG0 COM3 Common COM2 Output COM1...
Page 335: Lcd Controller Operation
LCD Controller Operation 18.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operation of LCD controller is discussed in the following sections. 18.2.1 LCD Memory The LCD memory map is shown in Figure 18−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode.
Page 336: Lcd Voltage Generation
18.2.4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33, R23, R13, and R03. Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in Table 18−1. The resistor value R is typically 680 kW.
Page 337: Static Mode
LCD Controller Operation 18.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 18−3 shows some example static waveforms. Figure 18−3. Example Static Waveforms COM0 Resulting Voltage for Segment a (COM0−SP1) Segment Is On.
Page 338 Figure 18−4 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−4. Static LCD Example Pinout and Connections Connections ’430 Pins...
Page 339 LCD Controller Operation Static Mode Software Example All eight segments of a digit are often located in four display memory bytes with the static display method. The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 340: Mux Mode
18.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 18−5 shows some example 2-mux waveforms. Figure 18−5. Mux Waveforms Example 2- COM1 COM0 Resulting Voltage for Segment h (COM0−SP2) Segment Is On.
Page 341 LCD Controller Operation Figure 18−6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−6.
Page 342 2-Mux Mode Software Example All eight segments of a digit are often located in two display memory bytes with the 2mux display rate The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table(Rx),Ry ;...
Page 343: Mux Mode
LCD Controller Operation 18.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 18−7 shows some example 3-mux waveforms. Figure 18−7. Mux Waveforms Example 3- COM2 COM1 COM0...
Page 344 Figure 18−8 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−8. 3-Mux LCD Example DIGIT10 Pinout and Connections Connections...
Page 345 LCD Controller Operation 3-Mux Mode Software Example The 3mux rate can support nine segments for each digit. The nine segments of a digit are located in 1 1/2 display memory bytes. LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the LSDigit of register of Rx.
Page 346: Mux Mode
18.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 18−9 shows some example 4-mux waveforms. Figure 18−9. Mux Waveforms Example 4- COM3 COM2 COM1 COM0...
Page 347 LCD Controller Operation Figure 18−10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 18−10. 4-Mux LCD Example DIGIT15 Pinout and Connections Connections...
Page 348 4-Mux Mode Software Example The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 349: Lcd Controller Registers
LCD Controller Operation 18.3 LCD Controller Registers The LCD Controller registers are listed in Table 18−2. Table 18−2.LCD Controller Registers Register LCD control register LCD memory 1 LCD memory 2 LCD memory 3 LCD memory 4 LCD memory 5 LCD memory 6 LCD memory 7 LCD memory 8 LCD memory 9...
Page 350 LCDCTL, LCD Control Register LCDPx rw−0 rw−0 rw−0 LCDPx Bits LCD Port Select. These bits select the pin function to be port I/O or LCD function for groups of segments pins. These bits ONLY affect pins with multiplexed functions. Dedicated LCD pins are always LCD function. 000 No multiplexed pins are LCD function 001 S0-S15 are LCD function 010 S0-S19 are LCD function...
Page 351: Lcd_A Controller
The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_A controller. The LCD_A controller is implemented on the MSP430x42x0 and MSP430F46xx devices. Topic 19.1 LCD Controller Introduction ....... . . 19.2 LCD Controller Operation .
Page 352: Lcd_A Controller Introduction
LCD_A Controller Introduction 19.1 LCD_A Controller Introduction The LCD_A controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: Display memory Automatic signal generation Configurable frame frequency...
Page 353 Figure 19−1. LCD_A Controller Block Diagram 0A4h Display Memory 8−bits 091h LCDSx LCDSON LCDFREQx f LCD Divider ACLK /32 .. /512 32768 Hz VLCDREFx VLCDx Regulated Charge Pump/ Contrast Control LCDCPEN LCDCAP/R33 LCDREF/ LCD_A Controller Introduction SEG39 SEG38 Segment Output Control SEG1 SEG0...
Page 354: Lcd_A Controller Operation
LCD_A Controller Operation 19.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup and operation of the LCD_A controller is discussed in the following sections. 19.2.1 LCD Memory The LCD memory map is shown in Figure 19−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode.
Page 355: Lcd_A Voltage And Bias Generation
19.2.3 LCD_A Voltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveform voltage, V1 be sourced from AV All internal voltage generation is disabled if the oscillator sourcing ACLK is turned off (OSCOFF = 1) or the LCD_A module is disabled (LCDON = 0). LCD Voltage Selection is sourced from AV 0.
Page 356 LCD_A Controller Operation To source the bias voltages V2 − V4 externally, REXT is set. This also disables the internal bias generation. Typically an equally weighted resistor divider is used with resistors ranging from 100 kW to 1 MW. When using an external resistor divider, the V pump when VLCDEXT = 0.
Page 357 The internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3 bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In static mode the internal divider is disabled. Some devices share the LCDCAP, R33, and R23 functions. In this case, the charge pump cannot be used together with an external resistor divider with 1/3 biasing.
Page 358: Lcd Timing Generation
LCD_A Controller Operation 19.2.4 LCD Timing Generation The LCD_A controller uses the f to generate the timing for common and segment lines. ACLK is assumed to be 32768 Hz for generating f LCDFREQx bits. The proper f requirement for framing frequency and the LCD multiplex rate and is calculated by: For example, to calculate f 30 - 100Hz:...
Page 359: Static Mode
19.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 19−4 shows some example static waveforms. Figure 19−4. Example Static Waveforms COM0 Resulting Voltage for Segment a (COM0−SP1) Segment Is On.
Page 360 LCD_A Controller Operation Figure 19−5 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−5. Static LCD Example Pinout and Connections Connections ’430 Pins...
Page 361 Static Mode Software Example All eight segments of a digit are often located in four display memory bytes with the static display method. The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx. MOV.B Table (Rx),RY MOV.B Ry,&LCDn MOV.B Ry,&LCDn+1...
Page 362: Mux Mode
LCD_A Controller Operation 19.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 19−6 shows some example 2-mux, 1/2 bias waveforms. Figure 19−6. Mux Waveforms Example 2- COM1 COM0 Resulting Voltage for...
Page 363 Figure 19−7 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−7. 2−Mux LCD Example DIGIT8 Pinout and Connections Connections...
Page 364 LCD_A Controller Operation 2-Mux Mode Software Example All eight segments of a digit are often located in two display memory bytes with the 2mux display rate The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 365: Mux Mode
19.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 19−8 shows some example 3-mux, 1/3 bias waveforms. Figure 19−8. Mux Waveforms Example 3- COM2 COM1 COM0 SP = Segment Pin...
Page 366 LCD_A Controller Operation Figure 19−9 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−9. 3-Mux LCD Example DIGIT10 Pinout and Connections Connections...
Page 367 3-Mux Mode Software Example The 3mux rate can support nine segments for each digit. The nine segments of a digit are located in 1 1/2 display memory bytes. LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the LSDigit of register of Rx.
Page 368: Mux Mode
LCD_A Controller Operation 19.2.9 4-Mux Mode In 3-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 19−10 shows some example 4-mux, 1/3 bias waveforms. Figure 19−10. Mux Waveforms Example 4- COM3...
Page 369 Figure 19−11 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 19−11.4-Mux LCD Example DIGIT15 Pinout and Connections Connections...
Page 370 LCD_A Controller Operation 4-Mux Mode Software Example The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 371: Lcd Controller Registers
19.3 LCD Controller Registers The LCD Controller registers are listed in Table 19−2. Table 19−2.LCD Controller Registers Register LCD_A control register LCD memory 1 LCD memory 2 LCD memory 3 LCD memory 4 LCD memory 5 LCD memory 6 LCD memory 7 LCD memory 8 LCD memory 9 LCD memory 10...
Page 372 LCD_A Controller Operation LCDACTL, LCD_A Control Register LCDFREQx rw−0 rw−0 rw−0 LCDFREQx Bits LCD Frequency Select. These bits select the ACLK divider for the LCD frequency. 000 Divide by 32 001 Divide by 64 010 Divide by 96 011 Divide by 128 100 Divide by 192 101 Divide by 256 110 Divide by 384...
Page 373 LCDAPCTL0, LCD_A Port Control Register 0 LCDS28 LCDS24 LCDS20 rw−0 rw−0 rw−0 LCDS28 Bit 7 LCD Segment 28 to 31 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. Multiplexed pins are port functions. Pins are LCD functions LCDS24 Bit 6...
Page 374 LCD_A Controller Operation LCDAPCTL1, LCD_A Port Control Register 1 Unused rw−0 rw−0 rw−0 Unused Bits Unused 7−2 LCDS36 Bit 1 LCD Segment 36 to 39 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function. Multiplexed pins are port functions.
Page 375 LCDAVCTL0, LCD_A Voltage Control Register 0 Unused R03EXT REXT rw−0 rw−0 rw−0 Unused Bit 7 Unused R03EXT Bit 6 V5 voltage select. This bit selects the external connection for the lowest LCD voltage. R03EXT is ignored if there is no R03 pin available. V5 is AV V5 is sourced from the R03 pin REXT...
Page 376 LCD_A Controller Operation LCDAVCTL1, LCD_A Voltage Control Register 1 Unused rw−0 rw−0 rw−0 Unused Bits Unused 7−5 VLCDx Bits Charge pump voltage select. LCDCPEN must be 1 for the charge pump to 4−1 be enabled. AV and VLCDEXT = 0. 0000 Charge pump disabled.
Page 377: Adc12
The ADC12 module is a high-performance 12-bit analog-to-digital converter. This chapter describes the ADC12. The ADC12 is implemented in the MSP430x43x and MSP430x44x devices. Topic 20.1 ADC12 Introduction ......... . 20.2 ADC12 Operation .
Page 378: Adc12 Introduction
ADC12 Introduction 20.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include: Greater than 200 ksps maximum conversion rate Monotonic 12-bit converter with no missing codes...
Page 379 Figure 20−1. ADC12 Block Diagram Ve REF+ V REF+ V REF− / Ve REF− INCHx 0000 SREF2 0001 0001 0010 0011 V R− Sample 0100 0101 12−bit SAR Hold 0110 0111 Convert 1000 1001 1010 1011 A12 † 1100 A13 † 1101 A14 †...
Page 380: Adc12 Operation
ADC12 Operation 20.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 20.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores programmable/selectable voltage levels (V lower limits of the conversion.
Page 381: Adc12 Inputs And Multiplexer
20.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 20−2. The input multiplexer is also a T-switch to minimize the coupling between channels.
Page 382: Voltage Reference Generator
ADC12 Operation 20.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin V Setting REFON=1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0.
Page 383: Sample And Conversion Timing
20.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: The ADC12SC bit The Timer_A Output Unit 1 The Timer_B Output Unit 0 The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit.
Page 384 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period The sampling timer keeps SAMPCON high after synchronization with sample.
Page 385 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t input resistance R by the source. The capacitor C of the source voltage V Figure 20−5.
Page 386: Conversion Memory
ADC12 Operation 20.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used.
Page 387 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 20−6 shows the flow of the Single-Channel, Single-Conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit.
Page 388 ADC12 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 20−7 shows the sequence-of-channels mode.
Page 389 Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 20−8 shows repeat-single-channel mode Figure 20−8.
Page 390 ADC12 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re-starts the sequence.
Page 391 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion.
Page 392: Using The Integrated Temperature Sensor
ADC12 Operation 20.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
Page 393: Adc12 Grounding And Noise Considerations
20.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry.
Page 394: Adc12 Interrupts
ADC12 Operation 20.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: ADC12IFG0-ADC12IFG15 ADC12OV, ADC12MEMx overflow ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set.
Page 395 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 396: Adc12 Registers
ADC12 Registers 20.3 ADC12 Registers The ADC12 registers are listed in Table 20−2 . Table 20−2.ADC12 Registers Register ADC12 control register 0 ADC12 control register 1 ADC12 interrupt flag register ADC12 interrupt enable register ADC12 interrupt vector word ADC12 memory 0 ADC12 memory 1 ADC12 memory 2 ADC12 memory 3...
Page 397 ADC12CTL0, ADC12 Control Register 0 SHT1x rw−(0) rw−(0) rw−(0) REF2_5V REFON rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 SHT1x Bits Sample-and-hold time. These bits define the number of ADC12CLK cycles in 15-12 the sampling period for registers ADC12MEM8 to ADC12MEM15. SHT0x Bits Sample-and-hold time.
Page 398 ADC12 Registers Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes. The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed.
Page 399 ADC12CTL1, ADC12 Control Register 1 CSTARTADDx rw−(0) rw−(0) rw−(0) ADC12DIVx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 CSTART Bits Conversion ADDx 15-12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15.
Page 400 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx ADC12OSC ACLK MCLK SMCLK CONSEQx Bits Conversion sequence mode select Single-channel, single-conversion Sequence-of-channels Repeat-single-channel Repeat-sequence-of-channels ADC12 Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation. BUSY No operation is active. A sequence, sample, or conversion is active.
Page 401 ADC12MCTLx, ADC12 Conversion Memory Control Registers SREFx rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 Bit 7 End of sequence. Indicates the last conversion in a sequence. Not end of sequence End of sequence SREFx Bits Select reference 000 V = AV 001 V 010 V...
Page 402 ADC12 Registers ADC12IE, ADC12 Interrupt Enable Register ADC12IE15 ADC12IE14 ADC12IE13 rw−(0) rw−(0) rw−(0) ADC12IE7 ADC12IE6 ADC12IE5 rw−(0) rw−(0) rw−(0) ADC12IEx Bits Interrupt enable. These bits enable or disable the interrupt request for the 15-0 ADC12IFGx bits. Interrupt disabled Interrupt enabled ADC12IFG, ADC12 Interrupt Flag Register ADC12 ADC12...
Page 403 ADC12IV, ADC12 Interrupt Vector Register r−(0) ADC12IVx Bits ADC12 interrupt vector value 15-0 ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h ADC12IVx r−(0) r−(0) r−(0) Interrupt Source Interrupt Flag No interrupt pending ADC12MEMx overflow...
Page 404 The SD16 module is a multichannel 16-bit, sigma-delta analog-to-digital converter. This chapter describes the SD16. The SD16 module is implemented in the MSP430FE42x and MSP430F42x devices. Topic 21.1 SD16 Introduction ......... . . 21.2 SD16 Operation .
Page 405: Sd16 Introduction
SD16 Introduction 21.1 SD16 Introduction The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully differential multiplexed inputs including a built-in temperature sensor. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters.
Page 406 Figure 21−1. SD16 Block Diagram V REF SD16VMIDON Temperature sensor Temperature sensor SD16INCHx A1.0 − SD16GAINx A1.1 − A1.2 − A1.3 − 1..32 A1.4 − A1.5 − A1.6 − A1.7 − SD16REFON Reference AV CC 1.2V SD16DIVx AV SS Divider 1/2/4/8 Reference Conversion Control...
Page 407: Sd16 Operation
SD16 Operation 21.2 SD16 Operation The SD16 module is configured with user software. The setup and operation of the SD16 is discussed in the following sections. 21.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency f stream is averaged by the digital filter for the conversion result.
Page 408: Channel Selection
21.2.5 Channel Selection Each SD16 channel can convert up to 8 differential pair inputs multiplexed into the PGA. Up to six input pairs (A0-A5) are available externally on the device. See the device-specific data sheet for analog input pin information. An internal temperature sensor is available to each channel using the A6 multiplexer input.
Page 409: Digital Filter
SD16 Operation 21.2.6 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC comb filter. The transfer function is described in the z-Domain by: H ( z ) + and in the frequency domain by: sinc OSRp H f + sinc p...
Page 410 Figure 21−3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
Page 411 SD16 Operation Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits. Figure 21−4 shows the digital filter output bits and their relation to SD16MEMx for each OSR. For example, for OSR = 256 and LSBACC = 1, the SD16MEMx register contains bits 23 −...
Page 412: Conversion Memory Registers: Sd16Memx
21.2.7 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversion results for each channel are moved to the corresponding SD16MEMx register with each decimation step of the digital filter. The SD16IFG bit for a given channel is set when new data is written to SD16MEMx.
Page 413: Conversion Modes
SD16 Operation 21.2.8 Conversion Modes The SD16 module can be configured for four modes of operation, listed in Table 21−2. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode. Table 21−2.Conversion Mode Summary SD16SNGL SD16GRP{ † A channel is grouped and is the master channel of the group when SD16GRP = 0 if SD16GRP for the prior channel(s) is set.
Page 414 Figure 21−6. Single Channel Operation Conversion Channel 0 SD16SNGL = 1 SD16GRP = 0 SD16SC Set by SW Channel 1 SD16SNGL = 1 SD16GRP = 0 SD16SC Conversion Channel 2 SD16SNGL = 0 SD16GRP = 0 Set by SW SD16SC = Result written to SD16MEMx Group of Channels, Single Conversion Consecutive SD16 channels can be grouped together with the SD16GRP bit...
Page 415 SD16 Operation Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set. SD16SC bits for all grouped channels will be automatically set and cleared with the master channel’s SD16SC bit.
Page 416: Conversion Operation Using Preload
21.2.9 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of f clock cycles and can range from 0 to 255.
Page 417 SD16 Operation Figure 21−9. Start of Conversion using Preload SD16OSRx = 32 f M cycles: SD16PRE0 = 8 Delayed Conversion SD16PRE1 = 0 Conversion 1 st Sample Ch1 Start of Conversion When channels are grouped, care must be taken when a channel or channels operate in single conversion mode or are disabled in software while the master channel remains active.
Page 418: Using The Integrated Temperature Sensor
21.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel SD16INCHx = 110. Any other configuration is done as if an external channel was selected, including SD16INTDLYx and SD16GAINx settings. The typical temperature sensor transfer function is shown in Figure 21−11. When switching inputs of an SD16 channel to the temperature sensor, adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are valid.
Page 419: Interrupt Handling
SD16 Operation 21.2.11 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: SD16IFG SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16 overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read.
Page 420 SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 421: Sd16 Registers
SD16 Registers 21.3 SD16 Registers The SD16 registers are listed in Table 21−3: Table 21−3.SD16 Registers Register SD16 Control SD16 Interrupt Vector SD16 Channel 0 Control SD16 Channel 0 Conversion Memory SD16 Channel 0 Input Control SD16 Channel 0 Preload SD16 Channel 1 Control SD16 Channel 1 Conversion Memory SD16 Channel 1 Input Control...
Page 422 SD16CTL, SD16 Control Register SD16DIVx SD16SSELx rw−0 rw−0 rw−0 Reserved Bits Reserved 15-9 SD16LP Bit 8 Low power mode. This bit selects a reduced speed, reduced power mode for the SD16. Low-power mode is disabled Low-power mode is enabled. The maximum clock frequency for the SD16 is reduced.
Page 423 SD16 Registers SD16CCTLx, SD16 Channel x Control Register Reserved SD16 SD16 SD16 LSBTOG LSBACC OVIFG rw−0 rw−0 rw−0 Reserved Bits Reserved 15-11 SD16SNGL Bit 10 Single conversion mode select Continuous conversion mode Single conversion mode SD16OSRx Bits Oversampling ratio SD16 Bit 7 LSB toggle.
Page 424 SD16IFG Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software. No interrupt pending Interrupt pending SD16SC Bit 1 SD16 start conversion No conversion start Start conversion...
Page 425 SD16 Registers SD16MEMx, SD16 Channel x Conversion Memory Register Conversion Bits Conversion Results. The SD16MEMx register holds the upper or lower Result 15-0 16-bits of the digital filter output, depending on the SD16LSBACC bit. SD16PREx, SD16 Channel x Preload Register rw−0 rw−0 rw−0...
Page 426 SD16IV, SD16 Interrupt Vector Register SD16IVx Bits SD16 interrupt vector value 15-0 SD16IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h † When an SD16 overflow occurs, the user must check all SD16CCTLx SD16OVIFG flags in order to determine which channel overflowed. SD16IVx r−0 r−0...
Page 427: Sd16_A
The SD16_A module is a single-converter 16-bit, sigma-delta analog-to-digital conversion module with high impedance input buffer. This chapter describes the SD16_A. The SD16_A module is implemented in the MSP430F42x0 devices. Topic 22.1 SD16_A Introduction ......... 22.2 SD16_A Operation .
Page 428: Sd16_A Introduction
SD16_A Introduction 22.1 SD16_A Introduction The SD16_A module consists of one sigma-delta analog-to-digital converter with an high impedance input buffer and an internal voltage reference. It has up to 8 fully differential multiplexed inputs including a built-in temperature sensor. The converter is based on a second-order oversampling sigma-delta modulator and digital decimation filter.
Page 429 Figure 22−1. SD16_A Block Diagram V REF Reference SD16VMIDON SD16INCHx − SD16BUFx − SD16GAINx − − 1..32 − − − − AVCC Temp. sensor SD16REFON Reference AV CC 1.2V SD16XDIVx SD16DIVx AV SS Divider Divider 1/2/4/8 1/3/16/48 Start Conversion Logic SD16OSRx 2 nd Order Modulator...
Page 430: Sd16_A Operation
SD16_A Operation 22.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 22.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency f stream is averaged by the digital filter for the conversion result.
Page 431: Analog Input Characteristics
22.2.5 Channel Selection The SD16_A can convert up to 8 differential pair inputs multiplexed into the PGA. Up to five input pairs (A0-A4) are available externally on the device. A resistive divider to measure the supply voltage is available using the A5 multiplexer input.
Page 432: Digital Filter
SD16_A Operation 22.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC comb filter. The transfer function is described in the z-Domain by: H ( z ) + and in the frequency domain by: sinc OSRp H f + sinc p...
Page 433 Figure 22−3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
Page 434 SD16_A Operation Digital Filter Output The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 22−4 shows the digital filter output and their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNI setting.
Page 435 OSR=256, LSBACC=1, SD16UNI=1 28 27 26 25 23 22 21 19 18 17 28 27 26 25 23 22 21 19 18 17 OSR=256, LSBACC=1, SD16UNI=0 28 27 26 25 23 22 21 19 18 17 28 27 26 25 23 22 21 19 18 17 28 27 26 25...
Page 436: Conversion Memory Register: Sd16Mem0
SD16_A Operation 22.2.8 Conversion Memory Register: SD16MEM0 The SD16MEM0 register is associated with the SD16_A channel. Conversion results are moved to the SD16MEM0 register with each decimation step of the digital filter. The SD16IFG bit is set when new data is written to SD16MEM0. SD16IFG is automatically cleared when SD16MEM0 is read by the CPU or may be cleared with software.
Page 437: Conversion Modes
22.2.9 Conversion Modes The SD16_A module can be configured for two modes of operation, listed in Table 22−3. The SD16SNGL bit selects the conversion mode. Table 22−3.Conversion Mode Summary SD16SNGL Single Conversion Setting the SD16SC bit of the channel initiates one conversion on that channel when SD16SNGL = 1.
Page 438: Using The Integrated Temperature Sensor
SD16_A Operation 22.2.10 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel SD16INCHx = 110. Any other configuration is done as if an external channel was selected, including SD16INTDLYx and SD16GAINx settings. The typical temperature sensor transfer function is shown in Figure 22−7.
Page 439: Interrupt Handling
22.2.11 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel: SD16IFG SD16OVIFG The SD16IFG bit is set when the SD16MEM0 memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16_A overflow condition occurs when a conversion result is written to SD16MEM0 location before the previous conversion result was read.
Page 440: Sd16_A Registers
SD16_A Registers 22.3 SD16_A Registers The SD16_A registers are listed in Table 22−4: Table 22−4.SD16_A Registers Register SD16_A Control SD16_A Interrupt Vector SD16_A Channel 0 Control SD16_A Conversion Memory SD16_A Input Control SD16_A Analog Enable 22-14 SD16_A Short Form Register Type Address SD16CTL Read/write 0100h...
Page 441 SD16CTL, SD16_A Control Register Reserved SD16DIVx SD16SSELx rw−0 rw−0 rw−0 Reserved Bits Reserved 15-12 SD16XDIV Bits SD16_A clock divider 11-9 000 /1 001 /3 010 /16 011 /48 1xx Reserved SD16LP Bit 8 Low power mode. This bit selects a reduced speed, reduced power mode Low-power mode is disabled Low-power mode is enabled.
Page 442 SD16_A Registers SD16CCTL0, SD16_A Control Register 0 Reserved SD16BUFx rw−0 rw−0 SD16 SD16 SD16 LSBTOG LSBACC OVIFG rw−0 rw−0 rw−0 Reserved Bit 15 Reserved SD16BUF Bits High impedance input buffer mode 14−13 Buffer disabled Slow speed/current Medium speed/current High speed/current SD16UNI Bit 12 Unipolar mode select...
Page 443 SD16 Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the LSBACC SD16_A conversion result. SD16MEMx contains the most significant 16-bits of the conversion. SD16MEMx contains the least significant 16-bits of the conversion. SD16OVIFG Bit 5 SD16_A overflow interrupt flag No overflow interrupt pending...
Page 444 SD16_A Registers SD16INCTL0, SD16_A Input Control Register SD16INTDLYx rw−0 rw−0 rw−0 SD16 Bits Interrupt delay generation after conversion start. These bits select the INTDLYx delay for the first interrupt after conversion start. Fourth sample causes interrupt Third sample causes interrupt Second sample causes interrupt First sample causes interrupt SD16GAINx...
Page 445 SD16MEM0, SD16_A Conversion Memory Register Conversion Bits Conversion Results. The SD16MEMx register holds the upper or lower Result 15-0 16-bits of the digital filter output, depending on the SD16LSBACC bit. SD16AE, SD16_A Analog Input Enable Register SD16AE7 SD16AE6 SD16AE5 rw−0 rw−0 rw−0 SD16AEx...
Page 446 SD16_A Registers SD16IV, SD16_A Interrupt Vector Register SD16IVx Bits SD16_A interrupt vector value 15-0 SD16IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 22-20 SD16_A SD16IVx r−0 r−0 r−0 Interrupt Source Interrupt Flag No interrupt pending − SD16MEMx overflow SD16CCTLx SD16OVIFG SD16_A Interrupt...
Page 447: Dac12
The DAC12 module is a 12-bit, voltage output digital-to-analog converter. This chapter describes the DAC12. Two DAC12 modules are implemented in the MSP430FG43x devices. Only DAC12_0 is implemented in MSP430x42x0 devices. Topic 23.1 DAC12 Introduction ......... . 23.2 DAC12 Operation .
Page 448: Dac12 Introduction
DAC12 Introduction 23.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
Page 449 Figure 23−1. DAC12 Block Diagram Ve REF+ To ADC12 module V REF+ 2.5V or 1.5V reference from ADC12 DAC12SREFx DAC12LSELx Latch Bypass DAC12GRP DAC12_0DAT Updated Group Load Logic DAC12SREFx DAC12LSELx Latch Bypass DAC12GRP DAC12_1DAT Updated DAC12AMPx DAC12IR AV SS V R− V R+ DAC12_0 DAC12_0Latch...
Page 450 DAC12 Introduction Figure 23−2. DAC12 Block Diagram For MSPx42x0 Devices V REF 1.2V reference from SD16 DAC12SREFx AV CC DAC12LSELx Latch Bypass DAC12GRP DAC12_0DAT Updated 23-4 DAC12 DAC12AMPx DAC12IR DAC12IR AV SS V R− V R+ DAC12_0 DAC12_0Latch DAC12_0DAT DAC12_0OUT DAC12RES DAC12DF...
Page 451: Dac12 Operation
23.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 23.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using the DAC12RES bit.
Page 452: Dac12 Reference
DAC12 Operation 23.2.2 DAC12 Reference On MSP430FG43x devices, the reference for the DAC12 is configured to use either an external reference voltage or the internal 1.5-V/2.5-V reference from the ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1} the V signal is used as the reference and when DAC12SREFx = {2,3} the REF+ signal is used as the reference.
Page 453: Dac12_Xdat Data Format
23.2.4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2’s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 23−3. Figure 23−3. Output Voltage vs DAC12 Data, 12-Bit, Straight Binary Mode Output Voltage Full-Scale Output When using 2’s compliment data format, the range is shifted such that a...
Page 454: Dac12 Output Amplifier Offset Calibration
DAC12 Operation 23.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the offset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so. The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 23−5.
Page 455: Grouping Multiple Dac12 Modules
23.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event. On the MSP430FG43x devices, DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0.
Page 456: Dac12 Interrupts
DAC12 Operation 23.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller. Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt. The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch.
Page 457: Dac12 Registers
23.3 DAC12 Registers The DAC12 registers are listed in Table 23−2. Table 23−2.DAC12 Registers Register DAC12_0 control DAC12_0 data DAC12_1 control DAC12_1 data Short Form Register Type Address DAC12_0CTL Read/write 01C0h DAC12_0DAT Read/write 01C8h DAC12_1CTL Read/write 01C2h DAC12_1DAT Read/write 01CAh DAC12 Registers Initial State Reset with POR...
Page 458 DAC12 Registers DAC12_xCTL, DAC12 Control Register DAC12OPS DAC12SREFx rw−(0) rw−(0) rw−(0) DAC12AMPx rw−(0) rw−(0) rw−(0) Modifiable only when DAC12ENC = 0 DAC12OPS Bit 15 DAC12 output select for MSP430FG43x and MSP430x42x0 devices. This bit is reserved on all other devices. MSP430FG43x Devices: DAC12_0 output on P6.6, DAC12_1 output on P6.7 DAC12_0 output on VeREF+, DAC12_1 output on P5.1...
Page 459 DAC12 Bit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence CALON and is automatically reset when the calibration completes. Calibration is not active Initiate calibration/calibration in progress DAC12IR Bit 8 DAC12 input range. This bit sets the reference input and voltage output range. DAC12 full-scale output = 3x reference voltage DAC12 full-scale output = 1x reference voltage DAC12...
Page 460 DAC12 Registers DAC12_xDAT, DAC12 Data Register r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) Unused Bits Unused. These bits are always 0 and do not affect the DAC12 core. 15-12 DAC12 Data Bits DAC12 data 11-0 DAC12 Data Format 12-bit binary 12-bit 2’s complement 8-bit binary 8-bit 2’s complement 23-14...
Page 461 The Scan IF peripheral automatically scans sensors and measures linear or rotational motion. This chapter describes the Scan interface. The Scan IF is implemented in the MSP430FW42x devices. Topic 24.1 Scan IF Introduction ......... . 24.2 Scan IF Operation .
Page 462: Scan If Introduction
Scan IF Introduction 24.1 Scan IF Introduction The Scan IF module is used to automatically measure linear or rotational motion with the lowest possible power consumption. The Scan IF consists of three blocks: the analog front end (AFE), the processing state machine (PSM), and the timing state machine (TSM).
Page 463 Figure 24−1. Scan IF Block Diagram SIFCI SIFCI3 SIFCI2 SIFCI1 SIFCI0 SIFCH3 SIFCH2 Excit SIFCH1 SIFCH0 SIFCOM DAC 10 Bit SIFVSS w/ RAM Scan I/F Analog Front−End (AFE) Processing State Machine (PSM) − Timing State Machine (TSM) w/ oscillator Scan IF Introduction To Timer_A Interrupt Request...
Page 464: Scan If Operation
Scan IF Operation 24.2 Scan IF Operation The Scan IF is configured with user software. The setup and operation of the Scan IF is discussed in the following sections. 24.2.1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement. The analog front end is automatically controlled by the timing state machine according to the information in the timing state machine table.
Page 465 Figure 24−2. Scan IF Analog Front End Block Diagram SIFCI SIFCI3 SIFCI2 SIFCI1 SIFCI0 SIFVSS Sample/Hold SIFCH3 SIFCH2 SIFCH1 SIFCH0 SIFTEN Excitation Excit Excit Excit Excit SIFLCEN(tsm) SIFEX(tsm) SIFVCC2 SIFCOM VMID SIFCISEL SIFCACI3 SIFRSON(tsm) SIFCA(tsm) SIFCAON SIFCAX SIFSH − SIFDAC(tsm) SIFDACON DAC 10 Bit SIFDACR0...
Page 466 Scan IF Operation Excitation The excitation circuitry is used to excite the LC sensors or to power the resistor dividers. The excitation circuitry is shown in Figure 24−3 for one LC sensor connected. When the SIFTEN bit is set and the SIFSH bit is cleared the excitation circuitry is enabled and the sample-and-hold circuitry is disabled.
Page 467 Figure 24−3. Excitation and Sample-And-Hold Circuitry SIFCH0 SIFVSS SIFCOM SIFEX(tsm) SIFLCEN(tsm) SIFTEN SIFVCC2 VMID Gen Sample-and-Hold Damping Excitation Excitation Scan IF Operation SIFSH Comparator From Channel Select Logic Scan IF 24-7...
Page 468 Scan IF Operation Sample-And-Hold The sample-and-hold is used to sample the sensor voltage to be measured. The sample-and-hold circuitry is shown in Figure 24−3. When SIFSH = 1 and SIFTEN = 0 the sample-and-hold circuitry is enabled and the excitation circuitry and mid-voltage generator are disabled.
Page 469 Direct Analog And Digital Inputs By setting the SIFCAX bit, external analog or digital signals can be connected directly to the comparator through the SIFCIx inputs. This allows measurement capabilities for optical encoders and other sensors. Comparator Input Selection And Output Bit Selection The SIFCAX and SIFSH bits select between the SIFCIx channels and the SIFCHx channels for the comparator input as described in Table 24−1.
Page 470 Scan IF Operation When SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIx channels and the SIFCI input allowing storage of the comparator output for one input signal into the four output bits SIF0OUT - SIF3OUT. This can be used to observe the envelope function of sensors.
Page 471 Scan IF Operation Comparator and DAC The analog input signals are converted into digital signals by the comparator and the programmable 10-bit DAC. The comparator compares the selected analog signal to a reference voltage generated by the DAC. If the voltage is above the reference the comparator output will be high.
Page 472 Scan IF Operation For each input there are two DAC registers to set the reference level as listed in Table 24−3. Together with the last stored output of the comparator, SIFxOUT, the two levels can be used as an analog hysteresis as shown in Figure 24−6.
Page 473 Internal Signal Connections to Timer1_A5 The outputs of the analog front end are connected to 3 different capture/compare registers of Timer1_A5. The output stage of the analog front end, shown in Figure 24−7. provides two different modes that are selected by the SIFCS bit and provides the SIFOx signals to Timer1_A5.
Page 474: Scan If Timing State Machine
Scan IF Operation 24.2.2 Scan IF Timing State Machine The TSM is a sequential state machine that cycles through the SIFTSMx registers and controls the analog front end and sensor excitation automatically with no CPU intervention. The states are defined within a 24 x 16-bit memory, SIFTSM0 to SIFTSM23.
Page 475 Figure 24−8. Timing State Machine Block Diagram SIFDIV3Ax SIFDIV2x SIFDIV3Bx Divider Divider ACLK /2 .. /450 /1/2/4/8 SIFEN SIFTSMRP Start ACLK State Pointer SIFDIV1x SIFCLKEN Control SMCLK Divider SIFCLK /1/2/4/8 Stop SIFACLK SIFREPEATx SIFFNOM SIFCLKFQx SIFOSC Enable SIFCNT3 Scan IF Operation SIFTSM0 SIFTSM1 SIFCH0...
Page 476 Scan IF Operation TSM Operation The TSM state machine automatically starts and re-starts periodically based on a divided ACLK start signal selected with the SIFDIV2x bits the SIFDIV3Ax and SIFDIV3Bx bits when SIFTSMRP = 0. For example, if SIFDIV3A and SIFDIV3B are configured to 270 ACLK cycles, then the TSM automatically starts every 270 ACLK cycles.
Page 477 TSM State Clock Source Select The TSM clock source is individually configurable for each state. The TSM can be clocked from ACLK or a high frequency clock selected with the SIFACLK bit. When SIFACLK = 1, ACLK is used for the state, and when SIFACLK = 0, the high frequency clock is used.
Page 478 Scan IF Operation TSM Test Cycles For calibration purposes, to detect sensor drift, or to measure signals other than the sensor signals, a test cycle may be inserted between TSM cycles by setting the SIFTESTD bit. The time between the TSM cycles is not altered by the test cycle insertion as shown in Figure 24−9.
Page 479 TSM Example Figure 24−10 shows an example for a TSM sequence. The TSMx register values for the example are shown in Table 24−6. ACLK and SIFCLK are not drawn to scale. The TSM sequence starts with SIFTSM0 and ends with a set SIFSTOP bit in SIFTSM9.
Page 480: Scan If Processing State Machine
Scan IF Operation 24.2.3 Scan IF Processing State Machine The PSM is a programmable state machine used to determine rotation and direction with its state table stored within MSP430 memory (flash, ROM, or RAM). The processing state machine measures rotation and controls interrupt generation based on the inputs from the timing state machine and the analog front-end.
Page 481 Figure 24−11.Scan IF Processing State Machine Block Diagram SIFS1x SIF0OUT SIF1OUT SIF2OUT SIF3OUT SIFS2x State Latch SIFQ6EN SIFQ7EN SISTOP(tsm) SIFPSMV PSM Operation At the falling edge of the SIFSTOP(tsm) signal the PSM moves the current-state byte from the PSM state table to the PSM output latch. The PSM has one dedicated channel of direct memory access (DMA), so all accesses to the PSM state table(s) are done automatically with no CPU intervention.
Page 482 Scan IF Operation The current-state and next-state logic are reset while the Scan IF is disabled. One of the bytes stored at addresses SIFPSMV to SIFPSMV + 3 will be loaded first depending on the S1 and S2 signals when the Scan IF is enabled. Signals S1 and S2 form a 2-bit offset added to the SIFPSMV contents to determine the first byte loaded to the PSM output latch.
Page 483 Scan IF Operation PSM Counters The PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updated with Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be read via the SIFCNT register. If the SIFCNTRST bit is set, each read access will reset the counters, otherwise the counters remain unchanged when read.
Page 484 Scan IF Operation Simplest State Machine Figure 24−12 shows the simplest state machine that can be realized with the PSM. The following code shows the corresponding state table and the PSM initialization. Figure 24−12. Simplest PSM State Diagram S1=1 & S2=0 S1=0 &...
Page 485 If the PSM is in state 01 of the simplest state machine and the PSM has loaded the corresponding byte at index 01h of the state table: For this example, S1 and S2 are set at the end of the next TSM sequence. To calculate the next state the bits Q5 - Q3 and Q0 of the state 01 table entry, together with the S1 and S2 signals are combined to form the next state: The state table entry for state 11 is loaded at the next state transition:...
Page 486: Scan If Debug Register
Scan IF Operation 24.2.4 Scan IF Debug Register The Scan IF peripheral has a SIFDEBUG register for debugging and development. Only the lower two bits should be written when writing to the SIFDEBUG register and only MOV instructions should be used write to SIFDEBUG.
Page 487: Scan If Interrupts
24.2.5 Scan IF Interrupts The Scan IF has one interrupt vector for seven interrupt flags listed in Table 24−7. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt.
Page 488: Using The Scan If With Lc Sensors
Scan IF Operation 24.2.6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a damping material to measure rotation. Rotation is measured with LC sensors by exciting the sensors and observing the resulting oscillation. The oscillation is either damped or un-damped by the rotating disk.
Page 489 24.2.6.1 LC-Sensor Oscillation Test The oscillation test tests if the amplitude of the oscillation after sensor excitation is above a reference level. The DAC is used to set the reference level for the comparator, and the comparator detects if the LC sensor oscillations are above or below the reference level.
Page 490 Scan IF Operation 24.2.6.2 LC-Sensor Envelope Test The envelop test measures the decay time of the oscillations after sensor excitation. The oscillation envelope is created by the diodes and RC filters. The DAC is used to set the reference level for the comparator, and the comparator detects if the oscillation envelop is above or below the reference level.
Page 491 Figure 24−17. LC Sensor Connections For The Envelope Test SIFCI SIFCI3 SIFCI2 SIFCI1 SIFCI0 SIFCH3 SIFCH2 SIFCH1 SIFCH0 SIFCOM 470 nF SIFVSS Power 470 nF Supply Terminals Scan IF Operation Scan IF 24-31...
Page 492: Using The Scan If With Resistive Sensors
Scan IF Operation 24.2.7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation. The damping material and magnets modify the electrical behavior of the sensor so that rotation and direction can be detected. Rotation is measured with resistive sensors by connecting the resistor dividers to ground for a short time allowing current flow through the dividers.
Page 493: Quadrature Decoding
24.2.8 Quadrature Decoding The Scan IF can be used to decode quadrature-encoded signals. Signals that are 90 out of phase with each other are said to be in quadrature. To Create the signals, two sensors are positioned depending on the slotting, or coating of the encoder disk.
Page 494 Scan IF Operation Figure 24−20. Quadrature Decoding State Diagram −1 Correct State Transitions To transfer the state encoding into counts it is necessary to decide what fraction of the rotation should be counted and on what state transitions. In this example only full rotations will be counted on the transition from state 00 to 01 or 10 using a 180 disk with the sensors 90 apart.
Page 495: Scan If Registers
24.3 Scan IF Registers The Scan IF registers are listed in Table 24−9. Table 24−9.Scan IF Registers Register Scan IF debug register Scan IF counter 1 and 2 Scan IF PSM vector Scan IF control 1 Scan IF control 2 Scan IF control 3 Scan IF control 4 Scan IF control 5...
Page 496 Scan IF Registers SIFDEBUG, Scan IF Debug Register, Write Mode Reserved Reserved Bits Reserved. Must be written as zero. 15-2 SIFDEBUGx Bits SIFDEBUG register mode. Writing these bits selects the read-mode of the SIFDEBUG register. SIFDEBUG must be written with MOV instructions only. When read, SIFDEBUG shows the last address read by the PSM When read, SIFDEBUG shows the value of the TSM state pointer and the PSM bits Q7 - Q0...
Page 497 SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written Unused Bits Unused. After 01h is written to SIFDEBUG, these bits are always read as zero. 15-13 TSM Index Bits When SIFDEBUG is read, after 01h is written to it, these bits show the TSM 12-8 register pointer index.
Page 498 Scan IF Registers SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written Active DAC Register Unused Bit 15 Unused. After 03h is written to SIFDEBUG, this bit is always read as zero. Bits When SIFDEBUG is read, after 03h is written to it, these bits show which DAC Register 14-12 register is currently selected to control the DAC.
Page 499 SIFCNT, Scan IF Counter Register r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) SIFCNT2x Bits SIFCNT2. These bits are the SIFCNT2 counter. SIFCNT2 is reset when 15-8 SIFEN = 0 or if read when SIFCNTRST = 1. SIFCNT1x Bits SIFCNT1. These bits are the SIFCNT1 counter. SIFCNT1 is reset when SIFEN = 0 or if read when SIFCNTRST = 1.
Page 500 Scan IF Registers SIFCTL1, Scan IF Control Register 1 SIFIE6 SIFIE5 SIFIE4 rw−(0) rw−(0) rw−(0) SIFIFG5 SIFIFG4 SIFIFG3 rw−(0) rw−(0) rw−(0) SIFIEx Bits Interrupt Enable. These bits enable or disable the interrupt request for the 15-9 SIFIFGx bits. Interrupt disabled Interrupt enabled SIFIFG6 Bit 8...
Page 501 SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by the SIFIFGSETx bits. SIFIFG0 must be reset with software. No interrupt pending Interrupt pending SIFTESTD Bit 1 Test cycle insertion. Setting this bit inserts a test cycle between TSM cycles. SIFTESTD is automatically reset at the end of the test cycle.
Page 502 Scan IF Registers SIFCTL2, Scan IF Control Register 2 SIFDACON SIFCAON SIFCAINV rw−(0) rw−(0) rw−(0) SIFSH SIFTEN SIFTCH1x rw−(0) rw−(0) rw−(0) SIFDACON Bit 15 DAC on. Setting this bit turns the DAC on regardless of the TSM control. The DAC is controlled by the TSM. The DAC is on.
Page 503 SIFVCC2 Bit 8 Mid-voltage generator /2 generator is off /2 generator is on if SIFSH = 0 SIFSH Bit 7 Sample-and-hold enable Sample-and-hold is disabled Sample-and-hold is enabled SIFTEN Bit 6 Excitation enable Excitation circuitry is disabled Excitation circuitry is enabled SIFTCH1x Bits These bits select the comparator input for test channel 1.
Page 504 Scan IF Registers SIFCTL3, Scan IF Control Register 3 SIFS2x SIFS1x rw−(0) rw−(0) rw−(0) SIFCS SIFIFGSETx rw−(0) rw−(0) rw−(0) SIFS2x Bits S2 source select. These bits select the S2 source for the PSM when SIFCS 15-14 = 1. SIF0OUT is the S2 source. SIF1OUT is the S2 source.
Page 505 SIFIFGSETx Bits SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set. 000 SIFIFG0 is set when SIF0OUT is set. 001 SIFIFG0 is set when SIF0OUT is reset. 010 SIFIFG0 is set when SIF1OUT is set. 011 SIFIFG0 is set when SIF1OUT is reset. 100 SIFIFG0 is set when SIF2OUT is set.
Page 506 Scan IF Registers SIFCTL4, Scan IF Control Register 4 SIFCNT1 SIFCNTRST SIFCNT2EN rw−(0) rw−(0) rw−(0) SIFDIV3Bx SIFDIV3Ax rw−(0) rw−(0) rw−(0) SIFCNTRST Bit 15 Counter reset. Setting this bit enables the SIFCNT register to be reset when it is read. SIFCNT register is not reset when read SIFCNT register is reset when it is read SIFCNT2EN Bit 14...
Page 507 SIFDIV3Bx Bits TSM start trigger ACLK divider. These bits together with the SIFDIV3Ax bits select the division rate for the TSM start trigger. SIFDIV3Ax Bits TSM start trigger ACLK divider. These bits together with the SIFDIV3Bx bits select the division rate for the TSM start trigger. The division rate is: SIFDIV3Bx SIFDIV2x Bits...
Page 508 Scan IF Registers SIFCTL5, Scan IF Control Register 5 rw−(0) rw−(0) rw−(0) SIFTSMRP SIFCLFQx rw−(0) rw−(1) rw−(0) SIFCNT3x Bits Internal oscillator counter. SIFCNT3 counts internal oscillator clock cycles 15-8 during one ACLK period when SIFFNOM = 0 or during four ACLK periods when SIFFNOM = 1 after SIFCLKGON and SIFCLKEN are both set SIFTSMRP Bit 7...
Page 509 SIFDACRx, Digital-To-Analog Converter Registers Unused Bits Unused. These bits are always read as zero, and when written, do not affect 15-10 the DAC output. DAC Data Bits 10-bit DAC data DAC Data Scan IF Registers DAC Data Scan IF 24-49...
Page 510 Scan IF Registers SIFTSMx, Scan IF Timing State Machine Registers SIFREPEATx rw−(0) rw−(0) rw−(0) SIFTESTS1 SIFRSON SIFCLKON rw−(0) rw−(0) rw−(0) Bits These bits together with the SIFACLK bit configure the duration of this state. REPEATx 15-11 SIFREPEATx selects the number of clock cycles for this state. The number of clock cycles = SIFREPEATx + 1.
Page 511 SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock source on for this state when SIFACLK = 1, even though the high frequency clock is not used for the TSM. When the high-frequency clock is sourced from the DCO, the DCO is forced on for this state, regardless of the MSP430 low-power mode.
Page 512 Scan IF Registers Processing State Machine Table Entry (MSP430 Memory Location) Bit 7 When Q7 = 1, SIFIFG6 will be set. When SIFQ6EN = 1 and SIFQ7EN = 1 and Q7 = 1, the PSM proceeds to the next state immediately, regardless of the SIFSTOP(tsm) signal and Q7 is used in the next-state calculation.

Texas Instruments MSP430x4xx User Manual

Introduction

Chapter 2

System Resets, Interrupts, and Operating Modes

System Reset and Initialization

Interrupts

Operating Modes

Principles for Low-Power Applications

Connection of Unused Pins

RISC 16-Bit CPU

Chapter 3

CPU Introduction

CPU Registers

Addressing Modes

Instruction Set

FLL+ Clock Module

Flash Memory Controller

Supply Voltage Supervisor

Hardware Multiplier

DMA Controller

Digital I/O

Watchdog Timer, Watchdog Timer+

Basic Timer1

Timer_A

Timer_B

USART Peripheral Interface, UART Mode

USART Peripheral Interface, SPI Mode

LCD_A Controller

Adc12

Sd16_A

Dac12

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