Channel Interrupt - Texas Instruments OMAP5912 Reference Manual

DSP DMA
Table 106. DMA Controller Operational Events and Associated Bits/Interrupts
Operational Event
Block transfer is complete.
Last frame transfer has
started.
Frame transfer is complete.
First half of current frame has
been transferred.
Synchronization event has
been dropped.
Time-out error has occurred.
4.17

Channel Interrupt

146 Direct Memory Access (DMA) Support
All interrupts generated by the DSP DMA controller are level-sensitive
interrupts, that is, the interrupt line is held active low for two DSP clock cycles
after the CPU reads the associated channel status register (see Table 106).
Interrupt Enable Bit
BLOCK_IE
LAST_IE
FRAME_IE
HALF_IE
DROP_IE
TIMEOUT_IE
Each of the six channels has its own interrupt. As shown in Figure 24, the
channel interrupt is the logical OR of all the enabled operational events except
the time-out event (the time-out event generates a bus-error interrupt request).
Choose any combination of these five events by setting or clearing the
appropriate interrupt enable (IE) bits in the interrupt control register
(DMA_CICR) for the channel. Determine which event(s) caused the interrupt
by reading the bits in the status register (DMA_CSR) for the channel.
Note:
The DMA interrupt status bits are set by hardware and cleared by a software
read operation to DMA_CSR. A subsequent DMA interrupt cannot be issued
until a program read of DMA_CSR has cleared the interrupt status bits. For
the ongoing operation of the DMA channel, the ISR must read the DMA_CSR
after each DMA interrupt.
Status Bit Associated Interrupt
BLOCK Channel interrupt
LAST Channel interrupt
FRAME Channel interrupt
HALF Channel interrupt
DROP Channel interrupt
TIMEOUT Bus-error interrupt
SPRU755B