Time-Out Conditions - Texas Instruments OMAP5912 Reference Manual

Figure 24. Triggering a Channel Interrupt Request
4.18

Time-Out Conditions

SPRU755B
DROP IE
DROP event
BLOCK IE
BLOCK event
FRAME IE
FRAME event
HALF IE
HALF event
LAST IE
LAST event
TIMEOUT IE
TIMEOUT event
For example, suppose you are monitoring activity in channel 1. In DMA_CICR:
DROP_IE = 1
-
HALF_IE = 0
-
FRAME_IE = 1
-
LAST_IE = 0
-
BLOCK_IE = 0
-
If a synchronization event is dropped or if the current frame transfer is done,
the channel 1 interrupt request is sent to the CPU. No other event can generate
the channel 1 interrupt. To determine whether one or both of the events
triggered the interrupt, read the drop and frame bits in DMA_CSR.
The channel 1 interrupt sets its corresponding flag bit in an interrupt flag
register of the CPU. The CPU can respond to the interrupt or ignore the
interrupt.
A time-out condition exists when a memory access has been stalled for too
many cycles. Each of the four standard ports of the DMA controller is
supported by hardware to detect a time-out condition:
DARAM port: A time-out counter in the DARAM port keeps track of how
-
many cycles have passed since a request was made to access the
DARAM. When the counter reaches 255 DSP clock cycles, the DARAM
port generates a time-out signal.
SARAM port: A time-out counter in the SARAM port keeps track of how
-
many cycles have passed since a request was made to access the
SARAM. When the counter reaches 255 DSP clock cycles, the SARAM
port generates a time-out signal.
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Direct Memory Access (DMA) Support
DSP DMA
Channel interrupt
147