Omap5912 Integration; Low-Dropout (Ldo) Voltage Regulator - Texas Instruments OMAP5912 Reference Manual

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OMAP5912 Clocks

External 32 kHz

OMAP3.2 gigacell

OMAP5912 Integration

RESPWRON_CORE

ULPD_PLL_CLKIN

ULPD_PLL_CLK

Dedicated power bus

After the power supplies have ramped up and the power-up reset has been

released, the LDO ramps up. When its output voltage is no more than 200 mV

below its final value, the LDO delivers a steady signal set to 1 to the ULPD. The

DPLL is configured in DPLL enable mode, as the LDO output voltage is stable.

Before entering low-power modes such as deep sleep and big sleep, the LDO

is put in sleep mode to reduce power dissipation. In that mode, the LDO

delivers a voltage derived from the VDD core through a pass-gate transistor.

Although the DPLL is in low-power mode, the DPLL settings stay the same.

In this configuration, the latency is reduced with returning to active mode.

The LDO can be powered down, where it behaves as a feed-through cell.

Power to the DPLL must be provided through an external power supply source.

This mode can also be a back-up mode if an external power supply is preferred

(see Table 1).

External system clock

Resets, clocks,

clock requests

Resets, clocks, wakeup

configuration

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