Wake-Up Interrupt; Fifo Interrupt Mode Operation - Texas Instruments OMAP5912 Reference Manual

Table 110. IrDA Mode Interrupts (Continued)
5 TX status
6 Receiver line
status interrupt
7 Received EOF

Wake-Up Interrupt

6.6.3

FIFO Interrupt Mode Operation

SPRU760B
1. THR empty before EOF sent. Last
bit of transmission of the IRDA frame
has occurred but with an underrun
error.
OR
2. Transmission of the last bit of the
IRDA frame is finished successfully.
CRC, ABORT or frame-length error is
written into STATUS FIFO
Received end-of-frame.
For IIR[5] the interrupt source 1 is used with interrupt reset method 1. The
interrupt source 2 is used with interrupt reset method 2.
Wake-up interrupt is a special interrupt, not designed the same as the previous
ones. It is enabled when the RX_CTS_DSR_WAKE_UP_ENABLE bit of the
supplementary control register (SCR[4]) is set to 1. The IIR register is not
modified when it occurs. SSR[1] must be checked to detect a wake-up event.
When wake-up interrupt occurs, the only way to clear it is to reset SCR[4] to
0.
In FIFO interrupt mode (FIFO control register FCR[0] = 1, relevant interrupts
enabled via IER), an interrupt signal (UART_nIRQ) informs the processor of
the receiver and transmitter status. These interrupts are raised when
receive/transmit FIFO thresholds (respectively, TLR[7:4] and TLR[3:0], or
FCR[7:6] and FCR[5:4]) are reached. The interrupt signals instruct the local
host to transfer data to the destination (from the UART module in receive mode
and/or from any source to the UART FIFO in transmit mode).
Note that when the UART flow control is enabled along with the interrupt
capabilities, the user must ensure that the UART flow control FIFO threshold
(TCR[3:0]) is greater than, or equal to, the receive FIFO threshold.
Figure 70 and Figure 71 respectively depict receive and transmit operations.
1. Read RESUME register.
OR
2. Read IIR
Read STATUS FIFO
[Read until empty—max 8 reads
required]
Read IIR
Serial Interfaces
UARTs
183