1X Ocp Master Port; Address Space; Arbiter Block; Buffer Block - Texas Instruments OMAP5912 Reference Manual

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1x OCP Master Port

Table 13. GDD/SSI Address Space

VLYNQ conf mapping

VLYNQ window mapping

The OCP interconnect arbiter 1x OCP master port has the following features:

OCP interface (master)

Balanced 100-MHz clock

32-bit data width only

Support 4x32 burst (4−2−2−LAST only) and non-burst accesses

Non-split burst only

This port is directly connected to the OMAP OCP_I slave interface.

The address space for the GDD/SSI and VLYNQ is shown in Table 13 (and is

fixed; no configuration registers are needed).

Start Address

The arbiter block controls the priority between GDD or VLYNQ and USB

conflicting requests to the OMAP OCP-I port. The arbitration scheme is

simple. If both 1x OCP and 1/2x OCP ports request at the same time, priority

is given to the 1x port. In other words, the GDD or VLYNQ always has the

highest priority.

The buffer block acts as a buffer between the input and output registers. This

block provides the buffering required to have all outputs come from the register

(no combinatorial output). Also, because the OMAP OCP_I interface does not

have the capability to handle split bursts, this buffer is used to provide burst

transaction without wait states (nonsplit burst) when bursts are initiated by the

USB OCP_I interface. The buffer block contains four registers to handle the

4 x 32 burst.

Peripheral Interconnects

OCP Interconnect

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