Dma Packed Channel Status Register For Compatible Mode - Texas Instruments OMAP5912 Reference Manual

System DMA
Table 28. Interrupt Mapping per LCh for Both Compatible Modes
Figure 11.

DMA Packed Channel Status Register for Compatible Mode

66 Direct Memory Access (DMA) Support
To control the mappings:
OMAP 3.2 Mapping: DMA_CCR.OMAP3_1_Mapping_Disable = 1
OMAP 3.1 Mapping: DMA_CCR.OMAP3_1_Mapping_Disable = 0
See the Multimedia Processor Interrupts Reference Guide (SPRU757) for
more details about interrupts.
Interrupt Line
MPU level 1 IRQ 19
MPU level 1 IRQ 20
MPU level 1 IRQ 21
MPU level 1 IRQ 22
MPU level 1 IRQ 23
MPU level 1 IRQ 24
MPU level 2 IRQ 53
MPU level 2 IRQ 54
MPU level 2 IRQ 55
MPU level 2 IRQ 56
MPU level 2 IRQ 57
MPU level 2 IRQ 58
MPU level 2 IRQ 59
MPU level 2 IRQ 60
MPU level 2 IRQ 61
MPU level 2 IRQ 62
MPU level 1 IRQ 25
In case of simultaneous events in two physical channels that share the same
interrupt line, only one interrupt is generated and all the relevant status bits are
set.
Each physical channel has a seven-bit status register. When an interrupt is
shared by two logical channels, the MPU can read the status from the two
channels in one TIPB access. The data read has the format shown in
Figure 11.
00 DMA_CSR [LCH_6] [6:0]
OMAP 3.2 Mapping
LCH_0
LCH_1
LCH_2
LCH_3
LCH_4
LCH_5
LCH_6
LCH_7
LCH_8
LCH_9
LCH_10
LCH_11
LCH_12
LCH_13
LCH_14
LCH_15
LCH_D
[13:7]
OMAP 3.1 Mapping
LCH_0 and LCH_6
LCH_1 and LCH_7
LCH_2 and LCH_8
LCH_3
LCH_4
LCH_5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LCH_12
[6:0]
DMA_CSR [LCH_0] [6:0]
SPRU755B