I/O Mapped Cache Control Registers - Texas Instruments OMAP5912 Reference Manual

Table 2. ST3 CPU Register (ST3)
Bit Name
15 CAFRZ
14 CAEN
13 CACLR
12:0
3.3.2

I/O Mapped Cache Control Registers

Table 3. Global Control Register (GCR)
Bit Name
15 Cut Clock
14 Auto Gating
13 Reserved
12 Flush Line
SPRU750A
Description
Instruction cache freeze
CAFRZ = 1: The cache contents are locked. In this mode, the cache contents
are not updated on a cache miss, but its contents still are available for cache
hits.
CAFRZ = 0: The cache contents can be unlocked: this is the default operating
mode of the cache. CAFRZ is cleared at reset.
Instruction cache enable
CAEN = 1: Program fetches either occur from the cache, from the internal
memory, or from the external memory through the external memory interface of
the device. Program fetches depend on the fetched program code addresses.
CAEN = 0: The cache controller never receives a program request, so all
program fetch requests are handled either by the internal memory or the
external memory. Default value after reset.
Instruction cache clear
CACLR = 1: The cache clear process is ongoing. During the cache clear
process, all the cache blocks are invalid.
CACLR = 0: The cache clear process is completed. CACLR bit is cleared by the
cache hardware upon completion of cache clear process. CACLR is cleared at
reset.
Not applicable (non-cache bits)
Table 3 through Table 9 describe the register bits.
Description
Stops I-cache control clock clock domain when I-cache is disabled
Enables automatic clock gating in EMIF interface clock domain,
active high
Flush the line specified by the flush line address register:
0: No flush
1: Flush the specified line; once the line flush occurs, the flush line
bit is automatically reset to 0.
DSP Memory
Access
R/W
R/W
R/W
DSP Subsystem 29