Figure 5.
Control of OMAP5912 Low-Power Output by ULPD POWER_CTRL_REG
POWER_CTRL_REG[DEEP_SLEEP_TRANSITION_EN (4)]
POWER_CTRL_REG[DVS_ENABLE(10)]
POWER_CTRL_REG[LOW_PWR_EN(0)]
1.9
Transitions Between Power Modes
SPRU753A
OMAP3.2
idle/wake-up
POWER_CTRL_REG[11]=0.
This feature allows dynamic control of the operating voltage of OMAP5912. It
provides two operating points (voltage, frequency) to adapt the operating
voltage to the performance requirement.
The OMAP3.2 DPLL frequency must be set accordingly before initiating the
procedure.
The DVS procedure described here goes through the OMAP3.2 idle and
wake-up sequences. To overcome limitations of this procedure, a more direct
way to control the OMAP5912 operating voltage is provided.
The user can directly force the LOW_PWR signal to 1 and thereby force the
operating voltage to 1.1 V by setting the bit POWER_CTRL_REG[1].
POWER_CTRL_REG [1] cannot force the LOW_PWR signal to 0 (see
Figure 5).
OSC12M_STOP
POWER_CTRL_REG[Min_Max_REG(11)]
Figure 6 shows the basic functional scheme of the FSM1:
procedure
must
0
1
POWER_CTRL_REG[LOW_PWR_REG(1)]
Power Management
Ultralow-Power Device
be
performed
with
LOW_PWR
23