Omap3.2 Dpll; Analog Phase-Locked Loop - Texas Instruments OMAP5912 Reference Manual

Analog Phase-Locked Loop

Table 3. APLL Mode Selection
APLL APLL APLL
SEL2 SEL1 SEL0
L L L
L H L
L H H
1.1.3

OMAP3.2 DPLL

2 Analog Phase-Locked Loop
16 Clocks
CLKIN CLKOUT APLL MODE
(MHz) (MHz)
19.2 96 Application mode 0
13 96 Application mode 2
12 96 Application mode 3
The reset value is 011, which selects APLL application mode 3. The
LOCK_STATUS flag in the ULPD_PLL_CTRL_STATUS register indicates that
the APLL has locked.
The internally generated 48-MHz clock or an external 48-MHz clock are
selected via the TEST_DBG_CTRL_0 bit in the OMAP5912 configuration. If
the TEST_DBG_CTRL_0 bit is set to 1, GPIO_14 becomes the source of the
48 MHz for the device.
The DPLL is controlled through the DPLL1_CTL_REG, which is mapped in the
OMAP3.2 register file. See Section 3, OMAP3.2 DPLL, for more detail.
The APLL is a clock multiplier for creating a 96-MHz clock from 12-MHz,
13-MHz, and 19.2-MHz input frequencies.
It includes an APLL circuit to generate an output clock, which is related to the
frequency of the input reference clock. The frequency multiplication factor is
an integer (12 MHz/19.2 MHz to 96 MHz) or a fractional (13 MHz−96 MHz):
-
In the integer multiplication scheme, the rising edge of the output clock is
synchronized to the rising edge of the input clock.
-
In the fractional multiplication scheme, the rising edge of the output clock
is not synchronized to the rising edge of the input clock for all input clock
periods. Nevertheless, the cell produces pulses to notify when the rising
edges of the input and output clocks coincide.
This output can be used to decimate the cycles where the phase relationship
between input and output clocks is unknown.
Dedicated power supply pins are required to isolate the core analog circuit
from the switching noise generated by the core logic that can cause jitter on
the clock output signal.
ULPD_PLL_CTRL_STATUS[2:0]
000
010
011
SPRU751A