96-Mhz Apll - Texas Instruments OMAP5912 Reference Manual

Table 1. LDO Control and Observability
LDO Mode
LDO in power-down
mode
LDO in sleep mode
LDO stable
1.1.2

96-MHz APLL

Table 2. Request for 48-MHz Clock
Request
CONF_MOD_UART1_CLK_MODE_R
CONF_MOD_UART2_CLK_MODE_R
CONF_MOD_UART3_CLK_MODE_R
CONF_MOD_USB_HOST_HHC_UHOST_
EN_R
USB_DPLL_MCLK_REQ
CONF_MOD_MMC_SD_CLK_REQ_R
CONF_MOD_MMC_SD2_CLK_REQ_R
CONF_CAM_CLKMUX_R
SPRU751A
Signal Register Bit Description
PWRDWN CONF_LDO_PWRDN_CNTRL_R
SLEEP SOFT_LDO_SLEEP
STEADY LDO_STEADY
The APLL is enabled whenever a clock request for a 48-MHz clock is active.
The clock request can be either hardware or software. The APLL generates
a 96-MHz clock, which is then divided by 2 in the ULPD module. An external
48-MHz clock can be selected by software if the APLL is not used.
Table 2 lists the different requests to activate the APLL. When no request is
active, the APLL is in power-down mode.
Source
OMAP5912 configuration
OMAP5912 configuration
OMAP5912 configuration
OMAP5912 configuration
USB OTG
OMAP5912 configuration
OMAP5912 configuration
OMAP 5912 configuration
The selection of the APLL modes is done in the ULPD module, as shown in
Table 3.
Notes
OMAP5912 configuration
ULPD register file
ULPD register file
Type of Destination
Request Module
Software UART1
Software UART2
Software UART3
Software USB OTG
Hardware USB OTG
Software MMC/SDIO1
Software MMC/SDIO2
Software Camera I/F
Clocks
Overview
15