Analog Phase-Locked Loop Control; Battery Failed Interrupt - Texas Instruments OMAP5912 Reference Manual

1.19

Analog Phase-Locked Loop Control

Figure 15. ULPD_PLL Clock Management
SYS_CLK_IN
Request for 48 MHz clock
Powerdown
APLL out clock
1.20

Battery Failed Interrupt

SPRU753A
If needed, the e-LDO can be tuned by adjusting SETUP_ANALOG_CELL2 in
oscillator mode or SETUP_ANALOG_CELL3 in external mode.
To provide a 48-MHz clock to peripherals that request it, the ULPD controls the
activation and deactivation of an on-chip analog phase-locked loop (APLL).
This APLL delivers a 96-MHz clock that is further divided inside the ULPD.
The ULPD enables APLL and its input clock whenever the system clock is
present and a 48-MHz clock request is active.
The APLL signals to the ULPD when it reaches lock state. By reading the
LOCK_STATUS bit in the ULPD_PLL_CTRL_STATUS register, the software
can determine whether the 48-MHz clocks are stable.
PLL clock
Note 1
time
Lock
See Section 4−2 for additional information on the APLL.
After releasing PWRON_RESET, RST_HOST_OUT is kept low for two 32-kHz
cycles, and then goes inactive high.
Ultralow-Power Device
Power Management 47