External 32-Khz Clock With Reset Mode 0 - Texas Instruments OMAP5912 Reference Manual

OMAP5912 Clock Architecture
5.3

External 32-kHz Clock with Reset Mode 0

34 Clocks
J
During power-on reset, the ULPD OSC1 delay timer is reset to 32 ms.
Thus, the system clock is not distributed before the timer reaches 0.
During this period, the device does not start operation (or transition out
of deep sleep state in the FSM of the ULPD). The ULPD OSC1 delay
timer can
SETUP_ANALOG_CELL3_REG after the power−on reset has
occurred.
The OMAP5912 32-kHz clock can be driven by an external squarewave clock.
See Figure 10 for the hardware connections of the external 32-kHz clock. This
figure applies to reset mode 0 only.
-
Hardware considerations:
J
The external clock is applied to the CLK32K_IN pin (ball P13).
J
OSC32K_IN must be tied to CVDDRTC (see Chapter 22 for a listing of
power supply voltages on OMAP5912).
J
OSC32K_OUT must be tied to VSS.
J
Ball Y13 can be connected to board ground (VSS).
-
Software considerations:
J
Set OSC32K_PWRDN_R to 1 in RTC_OSC_REG for power-saving
purposes.
be reprogrammed to 0 in the
SPRU751A