Interrupt Enable Register (Ier); Uart Modes Ier - Texas Instruments OMAP5912 Reference Manual

UARTs
Table 73. Modem Status Register (MSR) (Continued)
Bit Name
4 NCTS_STS
3 DCD_STS
2 RI_STS
1 DSR_STS
0 CTS_STS
6.3

Interrupt Enable Register (IER)

UART Modes IER

Table 74. Interrupt Enable Register (IER) (UART Mode)
Bit Name
7 CTS_IT
6 RTS_IT
5 XOFF_IT
4 SLEEP_MODE
156 Serial Interfaces
Function
This bit is the complement of the CTS input. In
loopback mode it is equivalent to MCR[1].
Indicates that DCD input (or MCR[3] in loopback)
has changed. Cleared on a read.
Indicates that RI input (or MCR[2] in loopback)
has changed state from low to high. Cleared on a
read.
1: Indicates that DSR input (or MCR[0] in
loop-back) has changed state. Cleared on a read.
1: Indicates that CTS input (or MCR[1] in
loopback) has changed state. Cleared on a read.
Offset Address (hex): 0x01 x S and LCR[7] = 0 (and EFR[4] = 1 for
IER[7:4]—UART modes only)
The interrupt enable register (IER) can be programmed to enable/disable any
interrupt. This mode has seven types of interrupt: Receiver error, RHR
interrupt, THR interrupt, XOFF received, and CTS/RTS change of state from
low to high. Each interrupt can be enabled/disabled individually. The IER also
has a sleep-mode enable bit.
Function
0: Disables the CTS interrupt.
1: Enables the CTS interrupt.
0: Disables the RTS interrupt.
1: Enables the RTS interrupt.
0: Disables the XOFF interrupt.
1: Enables the XOFF interrupt.
0: Disables sleep mode.
1: Enables sleep mode (stop baud rate clock when
the module is inactive).
R/W Reset
R Unknown
R 0
R 0
R 0
R 0
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
SPRU760B