Power-Up And Reset Management; Device Power Up - Texas Instruments OMAP5912 Reference Manual

Ultralow-Power Device
Table 6. Latencies for Each Peripheral (Continued)Clock (Continued)
Name Wake-Up Request
• CONF_MOD_MMC_SD_CLK_REQ_R
48 MHz for
MMCSDIO1
• SOFT_REQ_REG[12]
• CONF_MOD_MMC_SD2_CLK_REQ_R
48 MHz for
MMCSDIO2
• SOFT_REQ_REG[13]
• PWRON_RESET
CAM.EXCLK
• MPU_RST
• RTC_ON_NOFF
• 32-kHz watchdog time-out
• Wake-up request
• UART2 requests system clock
• PWRON_RESET
System clock for
GPIO
• MPU_RST
• RTC_ON_NOFF
• 32-kHz watchdog time-out
• Wake-up request
• UART2 requests system clock
1.15

Power-up and Reset Management

1.15.1

Device Power up

42 Power Management
The PWRON_RESET signal is the power-on reset and is used to reset the
ULPD 32-kHz logic and drive the input resets of OMAP3.2.
The PWRON_RESET is resynchronized on 32 kHz to achieve a clean reset
of the ULPD.
It is therefore required to maintain the power-on reset active low for a minimum
of two 32-kHz clock cycles.
At power-up reset, RESET_MODE selects between the external mode and the
oscillator mode.
-
If RESET_MODE is at 0, the ULPD starts in oscillator mode. In this case,
an on-chip oscillator generates the system input clock.
Time to Get the Clock Active
Depending on Initial FSM State
Deep Big
Sleep Sleep
T6 T5
T6 T5
T1 T2
T1 T2
SPRU753A
Awake
T5
T5