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5.1
Reset Modes and Clocking Options
Table 9.
Clocking Options with respect to Reset Modes
OSC1_IN support via crystal?
OSC1_IN support w/external clock source?
SYS_CLK_IN support w/external clock source?
OSC1_IN support via crystal?
OSC1_IN support w/external clock source?
SYS_CLK_IN support w/external clock source?
5.2
External System Clock with Reset Mode 0
SPRU751A
The ULPD (see chapter 6) manages transitions among deep sleep mode, big
sleep mode, and awake mode. Transitions are triggered by external events
(resets and clock requests) or by internal events (software reset, watchdog
time-out, and software clock requests). Some ULPD outputs can be sent to
external power management devices to adjust the OMAP5912 internal
corevoltage for optimum power dissipation, versus on-chip activity.
Reset mode 0 has several clocking options while reset mode 1 is much more
restrictive.
Reset Mode = 0
Reset Mode = 1
The OMAP5912 system clock can be driven at 12MHz, 13MHz, or 19.2MHz.
For an external system clock, the following hardware connections are used
(see Figure 10). Figure 10 applies to reset mode 0 only.
-
Hardware considerations:
J
The external clock is applied to the OSC1_IN pin (ball Y2).
J
The OSC1_OUT pin (ball W3) must be left unconnected.
-
Software considerations:
J
FUNC_MUX_CTRL_D(2:0) register bits should be 000 to ensure that
ball Y4 is not pin multiplexed as the SYS_CLK_IN.
J
Set CONF_OSC1_PWRDN_R to 1 in the MOD_CONF_CTRL_1
register so that the oscillator circuit is disabled, reducing power
consumption.
J
Set CONF_OSC1_GZ_R to 0 in MOD_CONF_CTRL_1 (when 1, this
bit disables square input clocks on the OSC1_IN pin).
OMAP5912 Clock Architecture
12 MHz
13 MHz
Yes
Yes
Yes
Yes
No
No
12 MHz
13 MHz
No
No
No
No
No
No
Clocks
19.2 MHz
Yes
Yes
No
19.2 MHz
No
No
Yes
33
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