Dsp Gdma Handler - Texas Instruments OMAP5912 Reference Manual

GDMA Handlers
Table 8. Functional Multiplexing MPU DMA F Register
(FUNC_MUX_ARM_DMA_F) (Continued)
Bit Name
11:6 CONF_ARM_DMA_REQ_27
5:0 CONF_ARM_DMA_REQ_26
Table 9. Functional Multiplexing MPU DMA G Register (FUNC_MUX_ARM_DMA_G)
Bit Name
31:6 RESERVED
5:0 CONF_ARM_DMA_REQ_31
2.2

DSP GDMA Handler

22 Direct Memory Access (DMA) Support
Function
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(27). n is between 0 and 55.
Writing value n in this register maps DMA
request source n+1 to system DMA controller
DMA_REQ(26). n is between 0 and 55.
Base Address = 0xFFFE 1000, Offset Address = 0x104
Function
Reserved.
Writing value n in this register maps
DMA request source n+1 to system
DMA controller DMA_REQ(31). n is
between 0 and 55
The various DSP and shared peripherals control up to 28 DMA requests,
whereas the DSP DMA in the OMAP3.2 can handle only 19 DMA requests.
The DSP GDMA handler acts as a crossbar so that each of the incoming DMA
requests can be remapped to any of the DSP DMA requests.
The mapping of each DMA request is done through the FUNC_DSP_DMA_x
registers located in the configuration module.
A 5-bit field is associated with each DSP channel so that any incoming DMA
request is remapped to the proper DSP DMA request.
The default configuration from reset ensures compatibility with the previous
OMAP5912 generation. Programmers have the flexibility to remap up to 19
requests according to the application task requirements. See Figure 2 for a
description of the DSP GDMA handler and Table 10 for DSP GDMA mapping.
R/W
R/W
R/W
.
R/W Reset
R/W 0x1A
R/W 0x19
Reset
0x0000000
0x1E
SPRU755B