Table of Contents
Advertisement
Restriction in Addressing With Multiplane Page Program
Figure 4.
Multi-Page Program Operation
t dbsy
R/B_
Address
80h
and data
2.1.4
Erase Operation
Table 4.
Programming Address for Erase Operation
Size of Flash Core
(MB)
32
SPRU756A
Although any block in each plane can be addressable for the multiplane page
program, the page address in the selected block must be the same. This
means that, given four addresses (one for each plane), bits 9 to 13 of those
addresses must be the same because bits 9 to 13 select the address of the
page in a block (see Figure 4).
It is impossible to start loading data in area B (upper half-page). The NFC does
not check the validity of addresses.
t dbsy
Address
11h
80h
and data
The command to mark the end of data is 0x10 for the last operation and 0x11
for the first accesses. If the program operation fails, the software takes the
responsibility to program the data in another page and mark the block (where
the page belongs) as invalid. After each address and data sent, there is a
latency time (T
). The actual programming of the flash occurs after the last
dbsy
address and data (T
prog
200 µs.
The erase operation (see Figure 5) is possible only at block level. Command
0x60 is driven with CLE high, then the address of the block to erase is driven
with ALE high, and the command 0xD0 is written with CLE high. During the
physical erase, the flash core drives R/B_ to low. When the erase operation
is completed, R/B_ returns to high. The command is repeatable up to four
times (depending on the NFMC, because this operation is valid on 1G bit and
512M bits, as shown in Table 13, Supported Operations on NFMCs
status of the erase operation can be checked with a read status operation
(command 0x70 or 0x71).
Block Address
Address Page in
(sent)
(sent but ignored)
A21-A13
t dbsy
Address
11h
80h
and data
). Typically, T
and T
dbsy
Start Address
Block
(not sent)
A12-A9
A7-A0
Memory Interfaces for the EMIFS
t prog
Address
11h
80h
and data
are, respectively ,1 µs and
prog
Erasable Block
Size
8K
Memory Interfaces
11h
.)
The
27
Advertisement
Chapters
Table of Contents
