Dma Power Reduction; Emulation Modes; Dma Controller Configuration Registers - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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DMA Power Reduction

Table 107. DMA Controller Configuration Registers

The timing of synchronization events (if the channel is synchronized). The

DMA controller cannot service a synchronized channel until the

synchronization event has occurred. For details, see Section 4.13,

Synchronizing Channel Activity.

The DSP is divided into idle domains that can be programmed to be idle or

active. The state of all five idle domains is called the idle configuration. Any idle

configuration that disables the clock generator domain and/or the DMA

domain stops the DMA clock and, therefore, stops activity in the DMA

controller. For more details, see Multimedia Processor OMAP3.2 Subsystem

Reference Guide (SPRU749) and Multimedia Processor Power Management

Reference Guide (SPRU753).

The FREE bit of DMA_GCR controls the behavior of the DMA controller when

a breakpoint is encountered in the debugger software. If FREE = 0 (the reset

value), a breakpoint suspends DMA transfers. If FREE = 1, DMA transfers are

not interrupted by a breakpoint.

Table 107 lists the DMA controller configuration registers. Table 108 through

Table 127 describe the register bits.

MPU Base Address(byte): 0xE100 3000 (note, Table 107 lists word offsets)

DSP Base Address (word): 0x00 1800

Global control

Global time-out control

Global software incompatible control

Channel 0 source destination parameters

Channel 0 control

Channel 0 interrupt control

Direct Memory Access (DMA) Support

Word Address

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