Set Status Bits (Ssb) - Texas Instruments OMAP5912 Reference Manual

I2C Multimaster Peripheral
Table 37. Test Mode Select

Set Status Bits (SSB)

SCL Line Sense Input Value (SCL_I)
86 Serial Interfaces
TMODE Mode
00 Functional mode (default)
01 Reserved
10 Test of SCL counters (SCLL, SCLH, PSC)
11 Loop back mode select + SDA/SCL IO mode select
Values after reset is low (2 bits).
SCL counter test mode: In this mode, the SCL pin is driven with a
-
permanent clock as if mastered, with the parameters set in the I2C_PSC,
I2C_SCLL, and I2C_SCLH registers.
Loopback mode: In the master transmit mode only, data transmitted out
-
of the I2C_DATA register (write action) is received in the same I2C_DATA
register via an internal path through the 1-deep FIFO buffers. The DMA
and interrupt requests are normally generated if enabled.
SDA/SCL IO mode: In this mode, the SCL IO and SDA IO are controlled
-
via the I2C_SYSTEST [3:0] register bits.
Writing 1 into this bit also sets the six read/clear-only status bits contained in
the I2C_STAT register (bits 5:0) to 1.
Writing 0 into this bit does not clear status bits that are already set; only writing
1 into a set status bit can clear it. This bit must be cleared before attempting
to clear a status bit.
0: No action
-
1: Set all six bits in I2C_STAT [5:0] to 1
-
Value after reset is low.
In normal functional mode (ST_EN = 0), this read-only bit always reads 0.
In system test mode (ST_EN = 1 & TMODE = 11), this read-only bit returns the
logical state taken by the SCL line (either 1 or 0).
Value after reset is low.
SPRU760B