Translation Process - Texas Instruments OMAP5912 Reference Manual

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Translation Process

The MPU software typically loads the TLB entries of the MMU before enabling

the MMU (Mmu_en bit in CNTL_REG).

When the MMU is disabled, no translation is done, the host addresses pass

through untranslated, and no permission checks or table walking are

The TLB contains the two embedded memories.

Each entry contains the logical address tag, the preserved bits, valid bits,

and page size.

Each entry contains the upper part of the associated physical address and

the access protection field.

The MPU can access the CAM and the RAM when hardware table walking

logic is disabled.

This section includes a brief introduction to MMU behavior. For more details,

see the MPU subsystem documentation.

The following page sizes are supported:

Section: 1M byte

Large page: 64K bytes

Small page: 4K bytes

Tiny page: 1K byte

The page size and the upper bits of the input (logical) address are used to

index the TLB CAM. Assuming there is a match (hit) in the CAM, the upper bits

of the output (physical) address are read from the associated TLB RAM entry.

These bits are then concatenated with the lower bits from the logical address.

The boundary of translated and untranslated bits is a function of the page size.

DSP Memory Management Unit

DSP Subsystem

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