Receive Interrupt; Transmit Interrupt - Texas Instruments OMAP5912 Reference Manual

Receive Interrupt

Figure 39. Receive Interrupt Timing Diagram
CLK
Channel N-1
T7 T6 T5
RXD
IT_RX
t < 2 x DSPXOR_CK (12 MHz)
(syn)
INTERRUPT_REG(3:0) = N−1

Transmit Interrupt

SPRU760B
The receive interrupt is generated every frame after the completion of the
reception of a data word:
In single-channel mode, the interrupt is generated one half-clock period
-
(plus a synchronization delay) after the reception of the word.
In multichannel mode, the interrupt is generated one half-clock period
-
(plus a synchronization delay) after the reception of the word of the
channel whose number is defined by the NB_CHAN_IT_RX parameter of
INTERRUPTS_REG register.
Note:
If MCSI is in slave mode, the clock must be driven after valid data reception
until the interrupt is generated and must not be gated before then, because
the interrupt is generated on the MCSI interface clock.
T4 T3 T2 T1 T0 T7
t
(syn)
The transmit interrupt is generated every frame after the start of the
transmission of a data word.
In single-channel mode, the interrupt is generated one clock period after
-
the beginning of the transmission of the word.
In multichannel mode, the interrupt is generated one clock period after the
-
transmission of the word of the channel whose number is defined by the
NB_CHAN_IT_RX parameter of INTERRUPTS_REG register.
T6 T5 T4 T3 T2 T1
Channel N
DSP_WRITE(1) => STATUS_REG(2)
Multichannel Serial Interfaces
Channel N+1
T0 T7 T6 T5 T4 T3
t
(syn)
Serial Interfaces
T2 T1 T0
119