32-Khz Synchronization Timer Registers - Texas Instruments OMAP5912 Reference Manual

5.2

32-kHz Synchronization Timer Registers

Table 47. 32-kHz Synchronization Timer Registers
Name Description
32KSYNCNT_REV Revision identification
RESERVED Reserved
RESERVED Reserved
RESERVED Reserved
CR Read counter
Table 48. Identification Register (32KSYNCNT_REV)
Base Address = 0xFFFB C400 (MPU), 0xE101 C400 (DSP)Offset = 0x00 (LSB), 0x02 (MSB)
Bit Name
31:8 RESERVED
7:0 CID_REV
Table 49. Read Counter Register (CR)
Base Address = 0xFFFB C400 (MPU), 0xE101 C400 (DSP)Offset = 0x10 (LSB), 0x12 (MSB)
Bit Name
15:0 COUNTER_LO
SPRU759B
Table 47 lists the 32-bit, 32-kHz synchronization registers, all of which are
accessible in 16-bit mode and use little-endian addressing. The address of a
register is the start address plus the offset address. Table 48 through Table 49
describe the register bits.
Base Address = 0xFFFB C400 (MPU), 0xE101 C400 (DSP)
Function
Reads return 0
Module HW revision number of the current timer
module: value set by hardware.
Four LSBs of TID_REV indicate a minor
revision.
Four MSBs of TID_REV indicate a major
revision.
Function
Value of 32-kHz SYNCH counter (16-bit LSB)
Same as CR[15:0]
32-kHz Synchronized Timer
Offset
LSB
R/W
R 0x00
R 0x04
R 0x08
R 0x0C
R 0x10
R/W
R HW ID revision
R/W
R
Timers
Offset
MSB
0x02
0x06
0x0A
0x0E
0x12
Reset
0x000000
Reset
0x0003
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