Scl High Time (Sclh) - Texas Instruments OMAP5912 Reference Manual

I2C Multimaster Peripheral

SCL High Time (SCLH)

Table 36. System Test Register (I2C_SYSTEST)
Bit Name
15 ST_EN
14 FREE
13:12 TMODE
11 SSB
10:4 −
3 SCL_I
2 SCL_O
1 SDA_I
0 SDA_O
84 Serial Interfaces
Master mode only.
This 8-bit value generates the SCL high-time value (t
is operated in master mode.
The SCL high time depends on the I2C_PSC value and the ICLK time period
(internal sampling clock rate):
When I2C_PSC = 0, t
-
When I2C_PSC = 1, t
-
When I2C_PSC > 1, t
-
The different values to compute the SCL high time are due to the
synchronization stage and noise filter on the SCL line.
Values after reset are low (all 8 bits).
Description
System test enable
Free running mode (on breakpoint)
Test mode select
Set status bits
Reserved
SCL line sense input value
SCL line drive output value
SDA line sense input value
SDA line drive output value
System Test Register
Never set this register for normal I
= (SCLH+7) * ICLK time period
HIGH
= (SCLH+6) * ICLK time period
HIGH
= (SCLH+5) * ICLK time period
HIGH
2
C operation.
) when the peripheral
HIGH
SPRU760B