Awake Mode; External Clock And Voltage Supply Control; Behavior Of Low_Pwr - Texas Instruments OMAP5912 Reference Manual

Ultralow-Power Device
1.5.3

Awake Mode

1.6

External Clock and Voltage Supply Control

1.6.1

Behavior of LOW_PWR

Figure 2. Assertion of LOW_PWR
CLK32K_IN
CK_REF
LOW_PWR
ULPD_STATE Awake state
20 Power Management
This mode has a shorter wake-up latency. It also provides clocks (system
frequency clocks and/or ULPD_PLL clock) to peripherals whenever requested
and while the OMAP3.2 input clock is stopped.
In awake mode, the OMAP input clock and any requested peripheral clocks
are active. In awake mode, the 32-kHz, system clock, OMAP input clock, and
any requested peripheral clocks are active.
The ULPD provides two signals to control the activation or the shut down of
the external clock and core voltage supplies.
These two signals, LOW_PWR and LOW_PWR, behave similarly except that
they do not have the same polarity.
LOW_PWR can be controlled by software, whereas LOW_PWR cannot.
The LOW_PWR signal is used in external clock mode.
When low, LOW_PWR indicates to external devices that the input system
clock (SYS_CLK_IN) can be shut down. It can also indicate to an external
power management device that the core voltage supply can be lowered to 1.1
V.
The LOW_PWR signal is asserted low when the ULPD enters the deep sleep
state (except at power-up reset) and released upon deep sleep exit (except
at power-up reset).
At power-up reset, LOW_PWR is reset to its inactive value (high).
Sleep sequence Deep sleep
SPRU753A