Dynamic Voltage Scaling; Low Voltage With Chip Totally Shut Down; Oscillator Clock Mode - Texas Instruments OMAP5912 Reference Manual

Table 51. DSP Isolation Control
12 ISOLATION_CONTROL
4

Dynamic Voltage Scaling

4.1

Low Voltage With Chip Totally Shut Down

4.1.1

Oscillator Clock Mode

SPRU753A
0: Electrical isolation inactive
1: Electrical isolation active
Reset of this bit is done upon power up reset only
(PWRON_RESET).
To minimize the leakage current when OMAP5912 is in deep sleep mode,
decrease the external supply voltages once the deep sleep state is validated.
The dynamic voltage scaling (DVS) feature enables the operation at reduced
clock frequency when the external supply voltages are low.
The OMAP5912 provides two signals that control the core voltage supplies
and activation or shutdown of the external clock, depending on the clock mode
(oscillator or external). These two signals, LOW_PWR and LOW_PWR,
behave similarly except that they do not have the same polarity, and
LOW_PWR can be controlled by software, whereas LOW_PWR cannot.
In deep sleep mode, to minimize the power consumption caused by leakage
currents, decrease the external supply voltages. To enable this feature, the
following conditions must be met:
-
Set the ULPD POWER_CTRL_REG[0] bit (LOW_PWR_EN field) to 1 to
enable the low-power feature.
-
Set the
(DEEP_SLEEP_TRANSITION_EN field) to 1 to enable transition to the
deep sleep state or to reset the POWER_CTRL_REG[10] bit to disable the
DVS feature.
If the above register settings are made, the external signal LOW_PWR
switches to active high whenever the ULPD enters the deep sleep state. In this
way, the external core voltage supply can be driven at low voltage, reducing
the leakage current.
When the ULPD exits the deep sleep state, the signal LOW_PWR switches
back to inactive low and the external core voltage supply ramps up to nominal
1.6 V.
At reset, the LOW_PWR feature is disabled and POWER_CTRL_REG[0] is
set to 0. The LOW_PWR signal is inactive low, which indicates nominal voltage
requirement. Figure 30 describes the behavior of the signal.
ULPD POWER_CTRL_REG[4]
Power Management
Dynamic Voltage Scaling
R/W 0x0
bit
93