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Figure 9.
Sleep Sequence
CLK32K_IN
CK_REF
(system clock)
CHIP_IDLE
(internal signal)
CHIP_WAKEUP
(internal signal)
LOW_PWR
ULPD_STATE
Awake state
1.13.2
Transition From Awake Mode to Big Sleep Mode
SPRU753A
Sleep
sequence
The sleep sequence requires three cycles of the CLK32K clock from assertion
of the CHIP_IDLE signal to assertion of the LOW_PWR signal.
Note:
The name of the signal CHIP_WAKEUP may confuse users. This signal is
not a wake-up signal but is an idle acknowledge.
Two necessary conditions lead to big sleep mode:
-
OMAP asserts the CHIP_IDLE (active high) when no clocks are needed
in OMAP3.2 or by any peripherals using OMAP3.2 output clocks.
-
At least one specific peripheral clock request is active or
POWER_CTRL_REG[4]=0
Sequence:
1) CHIP_IDLE is asserted high. There are active external clock requests or
POWER_CTRL_REG[4]=0.
2) OMAP3.2 input clock is disabled.
3) FSM1 enters the big sleep mode.
Ultralow-Power Device
Deep sleep or big sleep
Power Management
33
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