Logical Channel Scheduling - Texas Instruments OMAP5912 Reference Manual

System DMA
3.1.6

Logical Channel Scheduling

38 Direct Memory Access (DMA) Support
The system DMA port arbiters use a round robin scheme, but they are also
dependent on the LCh priority. For more information about LCh priority, see
the section on Logical Channel Priorities.
The arbiters use the following scheme each time the previous DMA port
access has finished:
1) Service all high-priority PChs using a round robin scheme. A low-priority
transfer currently being served by the same port is not aborted or
suspended by a high-priority transfer. The high-priority transfer waits.
Port arbitration is each-access based. If the current access is burst access,
then the arbitration is on the boundary of burst. The higher priority PCh
transfer takes the port as soon as the next available slot is open at the burst
boundary.
2) If no highly prioritized PCh is present, then all PCh are arbitrated/served
according to the round robin scheme.
A logical channel is marked as an active channel only when either of the
following conditions has been meet:
Case 1:
-
The logical channel is a synchronized channel.
J
The logical channel enable field is set.
J
The associated DMA request is triggered.
J
Case 2:
-
The logical channel is a nonsynchronized channel.
J
The logical channel enable field is set.
J
A logical channel can be assigned to a physical channel only when the logical
channel is active.
When a physical channel is granted, the DMA controller loads the physical
channel with the logical channel configuration register set, which controls the
data transfer through the system DMA. At the end of a channel transfer, the
current channel status is updated into the logical channel status register, and
the current logical channel enable is cleared if it is a nonsynchronized channel.
SPRU755B