I-Cache Performance; Hit Time; Miss Penalty - Texas Instruments OMAP5912 Reference Manual

3.6

I-Cache Performance

3.6.1

Hit Time

3.6.2

Miss Penalty

SPRU750A
All the line valid bits of the ½ ramset are then invalidated, as well as the TAG_
VALID bit.
The I-cache performances can be characterized by:
-
Average memory-access time = (Hit rate* Hit time) + (Miss rate * Miss
penalty.)
Hit time is described in Section 3.6.1 and miss penalty is described in Section
3.6.2.
The hit time is the time required for the I-cache to send back one instruction
when this instruction is present in the I-cache (cache hit).
The hit time falls under one of the following scenarios:
1) An initial request takes the first wait state.
2) A second request that is issued immediately after the first returns in 0 wait
states.
3) Subsequent requests that are consecutive and that are to sequential
addresses return in 0 wait states.
4) Subsequent requests that are not consecutive or do not fall in a sequential
address pattern are regarded as initial requests.
External memory accesses use burst reads to minimize latency for cache
misses. All the instructions can be sent back in one cycle after a latency of
several cycles for the first access.
The first access latency consists of:
-
First cycle: Request is received.
-
Fourth cycle: Request is forwarded to the EMIF after a cache miss.
-
X + 4 cycles: External memory access through the EMIF. Dependent on
memory speed and traffic controller loading.
-
X+5 cycles: EMIF returns ready.
-
X+6 cycles: I-cache returns ready.
DSP Memory
DSP Subsystem 37