Input Clock Enable; Timer Interrupts - Texas Instruments OMAP5912 Reference Manual

3.4.2 Configuration of the Input Clock for MPU 32-Bit OS Timers
3.4.3

Input Clock Enable

3.5

Timer Interrupts

SPRU759B
The input clock reference for the MPU timer modules is controlled from the
clock generation and reset module. Programming the ARM_TIMXO bit of the
MPU prescaler selection register ARM_CKCTL: in the clock module selects
between two possible clock sources.
Programming the ARM_TIMXO bit to 0 selects the main input reference
-
clock as the clock reference for the MPU timers.
Programming the ARM_TIMXO bit to 1 selects the output from the DPLL1
-
module as the source for the MPU 32-bit OS timers.
The default is referenced from DPLL1. When operating from DPLL1, it is
recommended to stop the MPU OS timer before programming a change to the
DPLL1 frequency divisor. See Clock Generation and Reset Management in
the Multimedia Processor OMAP 3.2 Subsystem Reference Guide
(SPRU749) for details of ARM_CKCTL: and on programming the DPLL1
module.
Input reference clocks for the DSP and MPU OS timer modules are ANDed
with a clock enable signal to gate the clock from timer internal logic. The clock
is enabled to the timers when the CLOCK_ENABLE bit is set in
DSP_CNTL_TIMER and in MPU_CNTL_TIMER.
An interrupt occurs when the corresponding timer decrements to zero.
DSP and MPU OS timer interrupt periods are defined by:
1) The programmed value for the DSP and MPU OS timer input clock
references (see Section 3.4.1 and Section 3.4.2).
2) The value of the prescaler bit field, PTV, in DSP_CNTL_TIMER and in
MPU_CNTL_TIMER. Table 16 lists valid entries for PTV.
3) The value of
DSP_LOAD_TIMER_LO, and MPU_LOAD_TIMER.
OMAP3.2 Operating System Timer
the load registers, DSP_LOAD_TIMER_HI,
Timers 23