Omap3.2 Embedded Ldo For Dpll[3] Control - Texas Instruments OMAP5912 Reference Manual

Ultralow-Power Device
Figure 14. OMAP3.2 Input Reset Generation
VDD / DVDDx
CLK32K_IN
PWRON_RESET
MPU_RST
CK_REF
Internal cold reset
Cold reset sequence for OMAP
Internal warm reset
1.18

OMAP3.2 Embedded LDO for DPLL[3] Control

46 Power Management
2 x sleep
Variable
clock
setup
time
An embedded LDO provides the DPLL of OMAP3.2 and the system clock
oscillator with a quiet voltage supply.
The ULPD manages the sleep transition of this e-LDO through the
LDO_SLEEP signal.
At reset, the e-LDO is not asleep.
At boot, the software can check that the e-LDO output voltage,
POWER_CTRL_REG [6], is stable before switching the DPLL to lock mode.
The e-LDO can be put to sleep permanently by software with
POWER_CTRL_REG [8] = 1. Before putting the e-LDO to sleep, the user must
first program the DPLL into bypass mode. The device can still run out of the
DPLL in bypass mode.
When POWER_CTRL_REG[7] = 1, the ULPD state machine automatically
powers down the e-LDO in deep sleep mode and powers it up on exit from
deep sleep mode. The ramp-up time of the e-LDO is hidden by the transition
time from deep sleep mode to awake mode.
30 x system clock
20 x system
30 x
clock
system
clock
Optional warm
reset
Optional warm reset
SPRU753A