Ulpd Input Clock Sources; Ulpd Setup Counters - Texas Instruments OMAP5912 Reference Manual

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Ultralow-Power Device
1.3

ULPD Input Clock Sources

1.4

ULPD Setup Counters

18
Power Management
-
The state machine (FSM1) manages the global power modes transitions.
It handles the idle/wake-up handshake with OMAP3.2 and monitors the
wake-up events.
The state machine controls the input system clock (internal oscillator or
external clock source) and generates resets to OMAP3.2 and to some pe-
ripherals. It also manages the power-up sequence. The FSM1 uses a set-
up timer to manage the sequencing of the wake-up procedure. Each setup
timer is associated with a specific analog cell.
-
The clock management module is composed of clock-gating logic,
multiplexers, and clock dividers. It generates and manages clocks to
OMAP3.2 and to some peripherals. It also manages the 48-MHz clocks.
Those clocks are generated from an on-chip analog phase locked loop
(APLL) operating at 96 MHz. The output of the APLL is divided by two to
create a 48-MHz reference clock. From the reference clock are derived the
various 48-MHz clocks.
-
The control register file is an MPU peripheral connected to the MPU
private peripheral bus; it is used to set/configure the features of ULPD.
See Section 1.24 for a detailed description of the registers.
The ULPD has two main clock sources: a 32-kHz clock and a system clock of
medium frequency (12 MHz, 13 MHz, and 19.2 MHz). These frequencies are
also the ULPD_PLL input clock frequency. See Chapter 5 for additional
information on the clock source for ULPD.
The ULPD can sequence the wake-up of the system from deep sleep properly
by enabling up to six analog cells successively (for example, oscillator and
regulator).
The ULPD FSM1 is instantiated in OMAP5912 with two setup counters, each
associated with an analog cell. Setup counters are cascaded and must be
programmed with the stabilization time of the associated analog cell.
Whenever a counter underflows, it enables the next analog cell and triggers
the associated counter.
The
cascaded
flow
SETUP_ANALOG_CELL2 and ends with SETUP_ANALOG_CELL3.
of
the
SETUP_ANALOG_CELL
starts
with
SPRU753A

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