32-Khz Watchdog Timer - Texas Instruments OMAP5912 Reference Manual

32-kHz Watchdog Timer

2 32-kHz Watchdog Timer
Table 15. Time-Out for 32-kHz Watchdog Timer
20 Timers
The software can access the 32-kHz watchdog at any time.
All writes to the watchdog register file are write posted, so the watchdog timer
write command is granted before the actual write in the timer clock domain is
performed.
This mode allows software to perform concurrent writes on 32-bit watchdog
registers and to manage them at software level by reading the status of posted
writes (by reading status bit of the write posted status register (WWPS)).
The prescaler value is forced to 1 at power up reset.
-
The WLDR value is forced to 0xFFF00000 at power up reset.
-
The timer input clock is 32 kHz.
-
Clock Frequency (kHz)
PTV
WLDR value
Reset period(s)
Default Configuration at
Power-Up Reset
PTV
WLDR value
The time-out value generates a reset that is logged into the ULPD reset status
register (Bit [3]).
After power-up reset, the time-out period can be changed by programming
either the prescaler (PTV) or the timer-load value (WLDR).
32
0
0xFFF0 0000
33
0
0xFFF0 0000
SPRU759B