Wake-Up Line Release; Timer Counting Rate - Texas Instruments OMAP5912 Reference Manual

Dual-Mode Timer
4.8.1

Wake-up Line Release

4.9

Timer Counting Rate

Table 30. Prescaler Clock Ratios Values
38 Timers
When the host processor receives a wake-up request issued by the timer
peripheral, the interface clock is reactivated, the host processor deactivates
the idle request signal, the timer deactivates the idle acknowledge signal, and
the host then can read the corresponding bit in TISR to find out which interrupt
source has triggered the wake-up request. After acknowledging the wake-up
request, the processor resets the status bit and releases the interrupt line by
writing a 1 in the corresponding bit of the TISR register.
The dual-mode timer is composed of a prescaler stage and a timer counter.
The prescaler stage is clocked with the timer clock and acts as a clock divider
for the timer counter stage.
The timer rate is defined by:
Value of the prescaler fields (PRE and PTV of TCLR register)
-
Value loaded into the timer load register (TLDR)
-
Table 30 lists prescaler clock ratios values.
timer rate = (0xFFFF FFFF – TLDR + 1) x timer clock period x clock divider (PS)
With timer clock period = 1/ timer clock frequency and PS = 2
For example, with a timer clock input of 32 kHz and a PRE field equal to 0, the
timer output period is as shown in Table 31.
PRE PTV Divisor (PS)
0 X
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1
2
4
8
16
32
64
128
256
(PTV + 1)
SPRU759B
.