Stop Sequence; Software Reset; Functional Mode Timing Diagrams; Single-Channel/Alternate Long Framing - Texas Instruments OMAP5912 Reference Manual

Stop Sequence

Software Reset

4.1.7

Functional Mode Timing Diagrams

Single-Channel/Alternate Long Framing

Figure 45. Single-Channel/Alternate Long Framing
CLK
FSYNCH
TXD
T7 T6
RXD
R7 R6
SPRU760B
A typical sequence to stop the interface is:
1) Disable MCSI clock: DSP_WRITE(0x0000) = CONTROL_REG
The status register keeps its content even after the stop of the transmis-
sion. The control registers can now be modified.
2) Software reset: DSP_WRITE(0x0002) = CONTROL_REG
The software reset initializes the status register.
The MCSI software reset is activated with the SW_RESET bit of the control
register (CONTROL_REG) (see Table 52, Activity Control Register).
This reset is limited to the control and status registers, the internal state
machine, and the PISO and SIPO logic. The parameters registers are not
affected by this software reset.
On the software reset, the MCSI reference clock is disabled, thus halting the
execution of any current operating mode.
The following timing diagrams are based on a positive clock polarity with
parameter CLOCK_POL = 0.
(Transmit on rising edge/receive on falling edge.)
T5 T4 T3 T2 T1
R5 R4 R3 R2 R1
First frame
T0 T7 T6 T5 T4
R0 R7 R6 R5 R4
Multichannel Serial Interfaces
T3 T2 T1 T0
R3 R2 R1 R0
Last frame
Serial Interfaces 125